OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 39

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

7.6
The serial channel interrupts are asserted on the PCI pin,
INTA#, by default. The interrupts can be enabled or
disabled using the GIS register interrupt mask (see section
6.4.5) and the IER register. Unlike generic 16C550
devices, the interrupt can not be disabled using the
implementation-specific MCR[3].
7.6.1
Serial channel interrupts are enabled using the Interrupt
Enable Register (‘IER’).
IER[0]: Receiver data available interrupt mask
logic 0 ⇒ Disable the receiver ready interrupt.
logic 1 ⇒ Enable the receiver ready interrupt.
IER[1]: Transmitter empty interrupt mask
logic 0 ⇒ Disable the transmitter empty interrupt.
logic 1 ⇒ Enable the transmitter empty interrupt.
IER[2]: Receiver status interrupt
Normal mode:
logic 0 ⇒ Disable the receiver status interrupt.
logic 1 ⇒ Enable the receiver status interrupt.
9-bit data mode:
logic 0 ⇒ Disable receiver status and address bit
logic 1 ⇒ Enable receiver status and address bit
In 9-bit mode (i.e. when NMR[0] is set), reception of a
character with the address-bit (i.e. 9
a level 1 interrupt if IER[2] is set.
IER[3]: Modem status interrupt mask
logic 0 ⇒ Disable the modem status interrupt.
logic 1 ⇒ Enable the modem status interrupt.
IER[4]: Sleep mode
logic 0 ⇒ Disable sleep mode.
logic 1 ⇒ Enable sleep mode whereby the internal clock
Sleep mode is described in section 7.6.4.
IER[5]: Special character interrupt mask or alternate
sleep mode
9-bit data framing mode:
logic 0 ⇒ Disable the received special character interrupt.
logic 1 ⇒ Enable the received special character interrupt.
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
Interrupts & Sleep Mode
Interrupt Enable Register ‘IER’
interrupt.
interrupt.
of the channel is switched off.
th
bit) set can generate
External-Free Release
In 9-bit data mode, The receiver can detect up to four
special characters programmed in the Special Character
Registers (see map on page 32). When IER[5] is set, a
level 5 interrupt is asserted when the receiver character
matches one of the values programmed.
650/950 modes (non-9-bit data framing):
logic 0 ⇒ Disable the special character receive interrupt.
logic 1 ⇒ Enable the special character receive interrupt.
In 16C650 compatible mode when the device is in
Enhanced mode (EFR[4]=1), this bit enables the detection
of special characters. It enables both the detection of
XOFF characters (when in-band flow control is enabled via
EFR[3:0]) and the detection of the XOFF2 special
character (when enabled via EFR[5]).
750 mode (non-9-bit data framing):
logic 0 ⇒ Disable alternate sleep mode.
logic 1 ⇒ Enable alternate sleep mode whereby the
In 16C750 compatible mode (i.e. non-Enhanced mode),
this bit is used an alternate sleep mode and has the same
effect as IER[4].
IER[6]: RTS interrupt mask
logic 0 ⇒ Disable the RTS interrupt.
logic 1 ⇒ Enable the RTS interrupt.
This enable is only operative in Enhanced mode
(EFR[4]=1). In non-Enhanced mode, RTS interrupt is
permanently enabled
IER[7]: CTS interrupt mask
logic 0 ⇒ Disable the CTS interrupt.
logic 1 ⇒ Enable the CTS interrupt.
This enable is only operative in Enhanced mode
(EFR[4]=1). In non-Enhanced mode, CTS interrupt is
permanently enabled.
internal clock of the channel is switched off.
OX16PCI952
Page 39