OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 58

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

9
The OX16PCI952 can be configured using an optional
serial electrically-erasable programmable read only
memory (EEPROM). If the EEPROM is not present, the
device will remain in its default configuration after reset.
Although this may be adequate for some applications,
many will benefit from the degree of programmability
afforded by this feature. The EEPROM also allows
accesses to the integrated UARTs and the parallel port,
which can be useful for default setups.
The EEPROM interface supports a variety of serial
EEPROM devices that have a proprietary serial interface
known as Microwire
supply the memory device with a clock, a chip-select, and
serial data input and output lines. In order to read from
such a device, a controller has to output serially a read
command and address, then input serially the data. The
interface controller has been designed to handle
(autodetect) the following list of compatible devices that
have a 16-bit data word format but differ in memory size
(and hence the number of address bits). NM93C46 (64
WORDS), NM93C56 (128 WORDS), devices with 256
WORDS, 512 WORDs and 1024 WORDS.
The OX16PCI952 incorporates a controller module which
reads data from the serial EEPROM and writes data into
the relevant register space. It performs this operation in a
sequence which starts immediately after a PCI bus reset
and ends either when the controller finds no EEPROM is
present or when it reaches the end of the eeprom data.
Note that any attempted PCI access while the eeprom is
being sensed or while data is being downloaded from the
serial EEPROM will result in a “retry” response. The
operation of this controller is described below.
Following device configuration, driver software can access
the serial EEPROM through four bits in the device-specific
Local Configuration Register LCC[27:24]. Software can use
this register to manipulate the device pins in order to read
and modify the EEPROM contents as desired. Any
changes to the eeprom contents, however, will not take
effect until a PCI bus reset takes place or until the eeprom
reload option (LCC[29]) is set.
A Windows® based utility to program the EEPROM is
available. For further details please contact Oxford
Semiconductor (see back cover).
Microwire
of Microwire
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
S
TM
ERIAL
TM
is a trade mark of National Semiconductor. For a description
, please refer to National Semiconductor data manuals.
EEPROM S
TM
. This interface has four pins which
PECIFICATION
External-Free Release
9.1
The serial EEPROM data is divided into five zones. The
size of each zone is an exact multiple of 16-bit WORDs.
Zone0 is allocated to the header. An EEPROM program
must contain a valid header before any further data is
interrogated.
The general EEPROM data structure is shown in Table 26.
9.1.1
The header identifies the EEPROM program as valid.
The programming data for each zone follows the
proceeding zone if it exists. For example a Header value of
0x950F indicates that all zones exist and they follow one
another in sequence (from Zone1 to Zone4), while 0x950A
indicates that only Zones 1 and 3 exist where the header
data is followed by Zone1 WORDs, and since Zone2 is
missing Zone1 WORDs are followed by Zone3 WORDs.
DATA
Zone
Bits
15:4
3
2
1
0
0
1
2
3
4
EEPROM Data Organisation
Description
These bits should return 0x950 to identify a valid
program. Once the OX16PCI952 reads 0x950
from these bits, it sets LCC[28] to indicate that a
valid EEPROM program is present.
1 = Zone1 (Function Access) exists
0 = Zone1 does not exist
1 = Zone2 (Local Configuration Registers) exists
0 = Zone2 does not exist
1 = Zone3 (Identification Registers) exists
0 = Zone3 does not exist
1 = Zone4 (PCI Configuration Registers) exists
0 = Zone4 does not exist
Zone0: Header
Size
(Words)
One
Multiples of 2
One to more
One to four
Two or more
Table 26: EEPROM data format
Description
Header
Function Access
Local Configuration Registers
Identification Registers
PCI Configuration Registers
OX16PCI952
Page 58