OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 20

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

6.4
The local configuration registers are a set of device specific registers that can be accessed from either function 0 or function 1.
They are mapped to the I/O and memory addresses set up in BAR2 and BAR3 of each function, with the offsets defined for each
register. I/O or memory accesses can be byte, word or dword accesses, however on little-endian systems such as Intel 80x86
the byte order will be reversed.
6.4.1
This register defines control of ancillary functions such as Power Management, Endian selection and the serial EEPROM. The
individual bits are described below.
DS-0028 Jul 05
Bits
0
1
2
4:3
6:5
23:7
24
25
26
27
28
OXFORD SEMICONDUCTOR LTD.
Accessing the Local Configuration Registers
Local Configuration and Control register ‘LCC’ (Offset 0x00)
Description
Mode. This bit returns the state of the MODE0 pin.
Test. This bit returns the state of the TEST pin.
Applications must tie the TEST pin to GND, so this bit will always return
‘0’.
Parallel Port Filter Enable.
This controls the noise filters on the parallel ports input control lines and
the data lines, of the parallel port and has meaning only when the
parallel port is available (Dual-mode device operation).
1 => Enable filters, 0 => disable filters.
Endian Byte-Lane Select for memory access to 8-bit peripherals.
00 = Select Data[7:0]
01 = Select Data[15:8]
Memory access to OX16PCI952 is always DWORD aligned. When
accessing 8-bit regions like the internal UARTs and the parallel port, this
option selects the active byte lane. As both PCI and PC architectures are
little endian, the default value will be used by systems, however, some
non-PC architectures may need to select the byte lane.
Power-down filter time.
These bits define a time value for the internal powerdown filter, part of
the power management circuitry of Function 0 (only). Once Function0 is
ready to go into the power down mode, the OX16PCI952 will wait for the
specified filter time and if Function0 is still indicating a power-down, it will
assert a powerdown request and a PCI interrupt (if the latter is enabled).
00 = power-down request disabled
01 = 4 seconds
Reserved. These bits are used for test purposes. The device driver must
write zeros to these bits.
EEPROM Clock. For reads or writes to the external EEPROM , toggle
this bit to generate an EEPROM clock (EE_CK pin).
EEPROM Chip Select. When set to 1, the EEPROM chip-select pin
EE_CS is activated (high). When set to 0, EE_CS is de-active (low).
EEPROM Data Out. For writes to the EEPROM, this output feeds the
data-input of the external EEPROM. This bit is output on the devices
EE_DO pin and clocked into the EEPROM by EE_CK.
EEPROM Data In. For reads from the EEPROM, this input bit is the
output-data (D0) of the external EEPROM connected to EE_DI pin.
EEPROM Valid.
A 1 indicates that a valid EEPROM program header is present
External-Free Release
10 = Select Data[23:16]
11 = Select Data[31:24]
10 = 129 seconds
11 = 515 seconds
EEPROM
Read/Write
W
W
W
-
-
-
-
-
-
-
-
PCI
RW
RW
RW
W
W
W
R
R
R
R
R
OX16PCI952
Reset
0000h
00
00
X
0
1
0
0
0
X
X
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