OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 26

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

6.6
The OX16PCI952 is compliant with the PCI Power
Management Specification Revision 1.0. Each logical
function implements its own set of Power Management
registers and supports the power states D0, D2 and D3.
Power management is accomplished by handling the
power-down and power-up (“power management event”)
requests, that are asserted on the relevant function’s
interrupt pin and the PME# pin respectively. Each function
can assert the PME# pin independently.
Power-down requests are not defined by any of the PCI
Power Management specifications. It is a device-specific
feature
implementation. The device driver can either implement the
power-down itself or use the special interrupt and power-
down features offered by the device to determine when the
function or device is ready for power-down.
It is worth noting that the PME# pin can, in certain cases,
activate the PME# signal when power is removed from the
device. This will cause the PC to wake up from Low-power
state D3(cold). To ensure full cross-compatibility with
system board implementations, the use of an isolator FET
is recommended (See Diagram). If Power Management
capabilities are not required, the PME# pin can be treated
as no-connect.
6.6.1
Provided that the necessary controls have been set in the
device’s local configuration registers (LCC, MIC, and GIS),
the internal UARTs and the 2 multi_purpose (MIO) pins can
be programmed to issue powerdown requests and/or
‘wakeup’ requests (power management events), for
function 0.
For the case of the 2 internal UARTs, function 0 can be
configured to monitor the activity of the serial channels,
and issue a power-down interrupt when both of the UARTs
DS-0028 Jul 05
PME#
OXFORD SEMICONDUCTOR LTD.
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Power Management
Power Management of Function 0
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PME#
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are inactive (no interrupts pending and both transmitters
and receivers are idle).
For the case when either or both of the MIO pins are
associated with function 0, the state of the MIO pin that
governs powerdown is the inverse of the MIO state that
asserts an interrupt on function 0’s interrupt pin (the INTA#
line) for normal functionality (if that option were to be
enabled). This means that when the MIO pins are not
interrupting, the MIO state will be taken as a powerdown
state.
When all powerdown sources of function 0 are indicating a
powerdown request (this means, both UARTs are
indicating a powerdown and each MIO pin associated with
function 0 is indicating a powerdown) only then will the
internal power management circuitry wait for a period of
time as programmed into the Power-Down Filter Time. This
time is defined by the local configuration register,
LCC[7:5]). If all function 0 powerdown requests remain
valid for this time (for the UARTs, this means that both
channels are still inactive) then the OX16PCI952 will issue
a powerdown interrupt on this function’s interrupt pin, if this
option is enabled. Alternatively, the device driver can poll
function 0’s powerdown status field in the local
configuration register GIS[22] to determine a powerdown
request. The powerdown filter stops the UARTs and any
MIO pins associated with function 0 from issuing too many
powerdown interrupts whenever the UARTs and MIO pin
activity is intermittent.
Upon a power down interrupt, the device driver can change
the power-state of the device (function 0) as required. Note
that the power-state of function 0 is only changed by the
device driver and at no point will the OX16PCI952 change
its own power state. The powerdown interrupt merely
informs the device driver that this logical function is ready
for power down. Before placing the device into the lower
power states, the driver must provide the means for the
function to generate a ‘wakeup’ (power management)
event.
Whenever the device driver changes function 0’s power-
state to state D2 or D3, the device takes the following
actions:
•
•
•
However, access to the configuration space is still enabled.
The internal clock to the internal UARTs is shut down.
PCI interrupts are disabled regardless of the values
contained in the GIS registers.
Access to I/O or Memory BARs is disabled.
OX16PCI952
Page 26