OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 10

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

Serial port pins (Contd)
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
Pins
106
109
109
109
110
100
108
107
107
105
105
96
99
99
99
98
97
97
95
95
Dir
1
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Name
DCD[0]#
DCD[1]#
DTR[0]#
DTR[1]#
485_En[0]
485_En[1]
Tx_Clk_Out[0]
Tx_Clk_Out[1]
RTS[0]#
RTS[1]#
CTS[0]#
CTS[1]#
DSR[0]#
DSR[1]#
Rx_Clk_In[0]
Rx_Clk_In[0]
RI[0]#
RI[1]#
Tx_Clk_In[0]
Tx_Clk_In[0]
External-Free Release
Description
Active-low modem “data-carrier-detect” input, for UART 0
and UART 1.
Active-low modem “data-terminal-ready output”, for UART 0
and UART 1.
If automated DTR# flow control is enabled for the
corresponding UART channel, the DTR# pin is asserted and
deasserted if the receiver FIFO reaches or falls below the
channel’s programmed thresholds, respectively.
In RS485 half-duplex mode, the DTR# pin of each UART
channel may be programmed to reflect the state of the
channel’s transmitter empty bit to automatically control the
direction of the RS485 transceiver buffer (see register
ACR[4:3])
Transmitter 1x clock (baud rate generator output).
For isochronous applications, the 1x (or Nx) transmitter clock
of each UART channel may be asserted on the DTR# pins
(see register CKS[5:4])
Active-low modem “request-to-send” output, for UART 0 and
UART 1.
If automated RTS# flow control is enabled for the
corresponding UART channel, the RTS# pin is deasserted
and reasserted whenever the receiver FIFO reaches or falls
below the programmed thresholds, respectively.
Active-low modem “clear-to-send” input, for UART 0 and
UART 1.
If automated CTS# flow control is enabled for the
corresponding UART channel, upon deassertion of the CTS#
pin, the channel’s transmitter will complete the current
character and enter the idle mode until the CTS# pin is
reasserted. Note: flow control characters are transmitted
regardless of the state of the CTS# pin.
Active-low modem “data-set-ready” input, for UART 0 and
UART 1.
If automated DSR# flow control is enabled for the
corresponding UART channel, upon deassertion of the
channel’s DSR# pin, the transmitter will complete the current
character and enter the idle mode until the DSR# pin is
reasserted. Note: flow control characters are transmitted
regardless of the state of the DSR# pin
External receiver clock input, for isochronous applications.
The DSR Uart pins are redefined as Rx_Clk_In, when the
corresponding UART channel’s CKS[1:0] register bits = ‘01’.
Active-low modem “Ring-Indicator” input, for UART 0 and
UART 1.
External transmitter clock.
The RI Uart pins are redefined as transmitter clk pins (and
thus used indirectly by the receiver) when the UART
channel’s CKS[6] register bit =’1’.
OX16PCI952
Page 10