OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 22

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

6.4.3
The receiver and transmitter FIFO levels of both UARTs is mirrored (shadowed) in this local configuration register, as follows.
6.4.4
The Interrupt Source Register of each UART and the general data status, is mirrored (shadowed) in this local configuration
register, as follows.
Good-Data status for a given internal UART is set when all of the following conditions are met:
•
•
•
If the device driver software reads a given channel’s receiver FIFO levels (from the UFL register) followed by the UIS register,
and the Good-Data status for that channel is set, the driver can remove the number of bytes indicated by the FIFO level without
the need to read the line status register of that channel. This feature enhances the driver efficiency.
For a given channel, if the Good-Data status bit is not set, then the software driver should examine the corresponding ISR bits.
If the ISR indicates a level 4 or higher interrupt, the interrupt is due to a change in the state of modem lines or detection of flow
control characters, for that channel. The device driver-software should then take appropriate measures as would in any other
550/950 driver. When ISR indicates a level 1 (receiver status) interrupt then the driver can examine the Line Status Register
(LSR) of the relevant channel. Since reading the LSR clears LSR[7], the device driver-software should either flush or empty the
contents of the receiver FIFO, otherwise the Good-Data status will no longer be valid.
The UART FIFO Level (UFL), the UART Interrupt Source register (UIS) and the Global Interrupt Status register (GIS) are
allocated adjacent address offsets (08h to 10h) in the Base Address Register. The device driver-software can read all of the
above registers in a single burst read operation. The location offset of the registers are such that the FIFO levels are usually read
before the status registers so that the status of the N characters indicated in the receiver FIFO levels are valid.
DS-0028 Jul 05
Bits
7:0
15:8
23:16
31:24
Bits
5:0
11:6
15:12
16
17
30:18
31
OXFORD SEMICONDUCTOR LTD.
ISR reads a level0 (no-interrupt pending), a level 2a (receiver data available), a level 2b (receiver time-out) or a level 3
(transmitter THR empty) interrupt
LSR[7] is clear so there is no parity error, framing error or break in the FIFO
LSR[1] is clear so no over-run error has occurred
UART FIFO Levels ‘UFL’ (Offset 0x08)
UART Interrupt Source Register ‘UIS’ (Offset 0x0C)
Description
UART0 Interrupt Source Register (ISR[5:0])
UART1 Interrupt Source Register (ISR[5:0])
Reserved
UART0 Good-Data Status
UART1 Good-Data Status
Reserved
Global Good-Data Status. This bit is the logical AND of bits 16 and 17,
i.e. it is set if Good-Data Status of all internal UARTs is set.
Description
UART0 Receiver FIFO Level (RFL[7:0])
UART1 Receiver FIFO Level (RFL[7:0])
UART0 Transmitter FIFO Level (TFL[7:0])
UART1 Transmitter FIFO Level (TFL[7:0])
External-Free Release
Read/Write
EEPROM
Read/Write
EEPROM
-
-
-
-
-
-
-
-
-
-
-
PCI
PCI
R
R
R
R
R
R
R
R
R
R
R
OX16PCI952
Reset
Reset
0x00h
0x00h
0x00h
0x00h
01h
01h
00h
Page 22
0h
1
1
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