OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 48

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

ASR[4]: Special character detected
logic 0 ⇒ No special character has been detected.
logic 1 ⇒ A special character has been received and is
This can be used to determine whether a level 5 interrupt
was caused by receiving a special character rather than an
XOFF. The flag is cleared following the read of the ASR.
ASR[5]: FIFOSEL
This bit reflects the unlatched state of the FIFOSEL pin.
ASR[6]: FIFO size
logic 0 ⇒ FIFOs are 16 deep if FCR[0] = 1.
logic 1 ⇒ FIFOs are 128 deep if FCR[0] = 1.
ASR[7]: Transmitter Idle
logic 0 ⇒ Transmitter is transmitting.
logic 1 ⇒ Transmitter is idle.
This bit reflects the state of the internal transmitter. It is set
when both the transmitter FIFO and shift register are
empty.
7.11.2 FIFO Fill levels ‘TFL & RFL’
The number of characters stored in the THR and RHR can
be determined by reading the TFL and RFL registers
respectively. When data transfer is in constant operation,
the values should be interpreted as follows:
1.
2.
7.11.3 Additional Control Register ‘ACR’
The ACR register is located at offset 0x00 of the ICR
ACR[0]: Receiver disable
logic 0 ⇒ The receiver is enabled, receiving data and
logic 1 ⇒ The receiver is disabled. The receiver
Changes to this bit will only be recognised following the
completion of any data reception pending.
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
The number of characters in the THR is no greater
than the value read back from TFL.
The number of characters in the RHR is no less than
the value read back from RFL.
stored in the RHR.
storing it in the RHR.
continues to operate as normal to maintain the
framing synchronisation with the receive data
stream but received data is not stored into the
RHR. In-band flow control characters continue
to be detected and acted upon. Special
characters will not be detected.
External-Free Release
ACR[1]: Transmitter disable
logic 0 ⇒ The transmitter is enabled, transmitting any
logic 1 ⇒ The transmitter is disabled. Any data in the
Changes to this bit will only be recognised following the
completion of any data transmission pending.
ACR[2]: Enable automatic DSR flow control
logic 0 ⇒ Normal. The state of the DSR# line does not
logic 1 ⇒ Data transmission is prevented whenever the
This bit provides another automatic out-of-band flow control
facility using the DSR# line.
ACR[4:3]: DTR# line configuration
When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the
transmitter 1x clock or the output of the baud rate
generator (Nx clock) are asserted on the DTR# pin,
otherwise the DTR# pin is defined as follows:
logic [00] ⇒ DTR# is compatible with 16C450, 16C550,
logic [01] ⇒ DTR# pin is used for out-of-band flow control.
logic [10] ⇒ DTR# pin is configured to drive the active-low
logic [11] ⇒ DTR# pin is configured to drive the active-
If the user sets ACR[4], then the DTR# line is controlled by
the status of the transmitter empty bit of LCR. When
ACR[4] is set, ACR[3] is used to select active high or active
low enable signals. In half-duplex systems using RS485
protocol, this facility enables the DTR# line to directly
control the enable signal of external 3-state line driver
buffers. When the transmitter is empty the DTR# would go
inactive once the SOUT line returns to it’s idle marking
state.
data in the THR.
THR is not transmitted but is held. However, in-
band flow control characters may still be
transmitted.
affect the flow control.
DSR# pin is held inactive high.
16C650 and 16C750 (i.e. normal).
It will be forced inactive high if the Receiver
FIFO Level (‘RFL’) reaches the upper flow
control threshold. DTR# line will be re-
activated (=0) when the RFL drops below the
lower threshold (see FCL & FCH).
enable pin of an external RS485 buffer. In
this configuration the DTR# pin will be forced
low whenever the transmitter is not empty
(LSR[6]=0), otherwise DTR# pin is high.
high enable pin of an external RS485 buffer.
In this configuration, the DTR# pin will be
forced high whenever the transmitter is not
empty (LSR[6]=0), otherwise DTR# pin is low.
OX16PCI952
Page 48