OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 19

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

6.3.2
IO space
When the dual-mode of the device is utilised, then BAR 0
and BAR 1 of function 1 are used to access the internal
Parallel Port through I/O transactions. Memory accesses to
the parallel port are not possible.
These I/O BARs correspond to the two sets of registers
defined to operate an IEEE1284 EPP and bi-directional
Parallel Port. BAR0 reserves an 8-byte block of I/O space
and BAR1 reserves a 4 byte-block of I/O space.
Once the I/O access enable bits in the Command register
(of this function’s PCI configuration space) are set, the
internal parallel port can be accessed using the mappings
shown in the following table. See section “Bi-Directional
Parallel Port” for more details.
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example:
BAR0 = 0x00000379 (8 bytes of I/O at address 0x378)
BAR1 = 0x00000779 (4 bytes of I/O at address 0x778)
If this relationship is not used, custom drivers will be
needed.
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
(Other modes)
Register
EcpDFifo
(EPP mode)
Register
ecpAFifo
EPPD1
EPPD2
EPPD3
EPPD4
Name
CnfgA
CnfgB
Name
EPPA
TFifo
ECR
PDR
DSR
DCR
PCI access to parallel port
-
BAR1 I/O Address Offset,
BAR 0 I/O Address Offset,
in Function 1
in Function 1
400h
400h
400h
401h
402h
403h
000h
000h
001h
001h
002h
003h
004h
005h
006h
007h
External-Free Release
.
OX16PCI952
Page 19