OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 71

• Manufacturer Part Number: OX16PCI952-TQAG
• Description: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

PCI CLK no (1
PCI CLK no (Retry Transaction)
1
5
8
7-8
11
14-15
17
1
5
Tslin (PCI clk to valid SLIN_N)
Tstb (PCI clk to valid STB_N)
Tpd (PCI clk to valid port Address) - 16ns max*
EPP Write Address Cycle duration is dependant upon the timing response of the peripheral’s BUSY line and the parallel port
filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the
host to the peripheral’s BUSY line when the filters are enabled.
* These values exclude the effects of external parasitic (board) capacitances.
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
st
Transaction)
- Start of PCI write to EPP Address register
- Start of EPP address write cycle on parallel port side.
- PCI transaction completes with a ‘retry’ (without affecting current EPP write address cycle) as EPP cycle cannot complete within 16 PCI CLK cycles
- Peripheral Asserts BUSY
- Host responds to BUSY by de-asserting SLIN_N (4 clock cycles after sampling BUSY)
- Peripheral Deasserts BUSY
- Host responds to BUSY by asserting SLIN_N and the parallel port data lines (2 clock cycles after sampling BUSY).
- EPP cycle completed.
- Start of Retry transaction, to the original write to EPP address register
- Retry transaction completes with “Data Transfer”, without initiating another EPP write address cycle.
- 16ns max*
- 16ns max*
Write to EPP Address Register (EPP Write Address cycle)
External-Free Release
OX16PCI952
Page 71