OX16PCI952-TQAG OXFORD [Oxford Semiconductor], OX16PCI952-TQAG Datasheet - Page 5

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OX16PCI952-TQAG

Manufacturer Part Number
OX16PCI952-TQAG
Description
Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
Manufacturer
OXFORD [Oxford Semiconductor]
Datasheet

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1
1.1
Higher degree of integration:
The
performance 16C950 UARTs and one IEEE1284 compliant
bi-directional parallel port.
UART device driver efficiency is increased by using each
channel’s features such as the 128-byte deep transmitter &
receiver FIFOs, flexible clock options, automatic flow
control, programmable interrupt and flow control trigger
levels and readable FIFO levels. Data rates of each UART
is up to 60Mbps.
DS-0028 Jul 05
OXFORD SEMICONDUCTOR LTD.
P
OX16PCI952
ERFORMANCE
Improvements of the OX16PCI952 over discrete solutions:
Table 1: OX16PCI952 performance compared with PCI Bridge + generic UART/Parallel Port Combinations.
DWORD access to UART Interrupt Source
Full Plug and Play with external EEPROM
No. of available external interrupt pins
Integral 1284 Compliant parallel port
Support for PCI Power Management
Zero wait-state read/write operation
Max baud rate in 1x clock mode
Max baud rate in normal mode
Readable status of flow control
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
External 1x baud rate clock
Transmitter empty interrupt
Multi-function PCI device
Registers & FIFO Levels
Clock prescaler options
Internal serial channels
offers
Auto DSR#/DTR# flow
Auto CTS#/RTS# flow
Readable FIFO levels
RS485 buffer enable
Auto Xon/Xoff flow
Good-Data status
C
9-bit data frames
Infra-red (IrDA)
Software reset
Rx/Tx disable
OMPARISON
Sleep mode
FIFO depth
Device ID
Feature
two
internal
ultra-high
External-Free Release
OX16PCI952
15 Mbps
60 Mbps
yes
yes
yes
yes
yes
yes
yes
yes
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
2
2
Improved access timing:
Access to the internal UARTs require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
The OX16PCI952 offers shadowed FIFO levels and
Interrupt status registers of the internal UARTs, as well as
general device interrupt status, to reduce the device driver
interrupt latency.
16C552 + PCI
115 Kbps
Bridge
yes
n/a
n/a
n/a
no
no
no
no
no
no
no
16
no
no
no
no
no
no
no
no
no
no
no
no
no
0
2
4
1
16C652 + PCI
1.5 Mbps
Bridge
yes
yes
yes
yes
yes
n/a
no
no
no
no
no
no
no
64
no
no
no
no
no
no
no
no
no
0
2
4
4
4
2
OX16PCI952
Page 5

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