SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 62

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
RESET
COND.
Bit 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps
and 300 Kbps are selected.
Bits 1 – 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See
corresponding to the individual data rates. The data rate select bits are unaffected by a software
reset, and are set to 250 Kbps after a hardware reset.
Bits 3 – 6
Always read as a logic “1”
Bit 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or
the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
MODEL 30 MODE
Bits 0 – 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See
to the individual data rates. The data rate select bits are unaffected by a software reset, and are set
to 250 Kbps after a hardware reset.
Bit 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
Bit 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
Bits 4 – 6
Always read as a logic “0”
Bit 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or
the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
7
DSK
CHG
N/A
UNDEFINED
UNDEFINED
6
0
0
5
0
0
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
4
0
0
46
3
DMAEN
0
Table 7.6
Table 7.6 on page 42
2
NOPREC
0
for the settings corresponding
1
DRATE
SEL1
1
for the settings
SMSC SCH311X
0
DRATE
SEL0
0
Datasheet