SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 183

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 19 Buffered PCI Outputs
APPLICATION NOTE: These outputs are note available on the SCH3116.
SMSC SCH311X
19.1
19.1.1
NAME
PCI_RESET#
nIDE_RSTDRV
nPCIRST1
nPCIRST2
nPCIRST3
NAME
Tf
DESCRIPTION
nIDE_RSTDRV high to low fall time. Measured form 90% to
10%
The SCH3112 and SCH3114 devices provide three software controlled PCIRST# outputs and one
buffered IDE Reset.
Table 19.1
IDE Reset Output
nIDE_RSTDRV is an open drain buffered copy of PCI_RESET#. This signal requires an external 1K Ω
pull-up to VCC or 5V. This pin is an output only pin which floats when VCC=0. The pin function’s default
state on VTR POR is the nIDE_RST function; however the pin function can be programmed to the a
GPO pin function by bit 2 in the PME_STS1 GPIO control register.
The nIDE_RSTDRV output has a programmable forced reset. The software control of the
programmable forced reset function is located in the GP4 GPIO Data register. When the GP44 bit (bit
4) is set, the nIDE_RSTDRV output follows the PCI_RESET# input; this is the default state on VTR
POR. When the GP44 bit is cleared, the nIDE_RSTDRV output stays low.
See GP44 and GP4 for Runtime Register Description
Buffered PCI Outputs Interface
PCI_RESET# (INPUT)
BUFFER
PCI_I
OD8
OP14
OP14
OP14
describes the interface.
0
1
Table 19.1 Buffered PCI outputs Interface
Table 19.2 nIDE_RSTDRV Truth Table
Table 19.3 nIDE_RSTDRV Timing
POWER WELL
VCC
VCC
VTR
VTR
VTR
DATASHEET
167
DESCRIPTION
PCI Reset Input
IDE Reset Output
Buffered PCI Reset Output
Buffered PCI Reset Output
Buffered PCI Reset Output
(Chapter 26, "Runtime Register," on page
nIDE_RSTDRV (OUTPUT)
MIN
Hi-Z
TYP
0
MAX
15
Rev 0.2 (09-28-04)
UNITS
ns
293).