SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 293
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SCH3112I-NE
Manufacturer Part Number
SCH3112I-NE
Description
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.SCH3112I-NE.pdf
(396 pages)
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LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
Device ID -
Hard wired
Default = 0x7C
on VCC POR,
VTR POR,
SOFT RESET and PCI
RESET
Device Rev
Hard wired
= Current Revision
Power Control
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and PCI
RESET
Reserved
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
OSC
Default = 0x44, on on
VCC POR,
VTR POR and
PCI RESET
Configuration Address
Byte 0
Default
=0x002E (Sysopt01=10)
=0x004E (Sysopt01=11)
on VCC POR and PCI
RESET
Configuration Address
Byte 1
Default
=0x162E (Sysopt01=00)
=0x164E (Sysopt01=01)
on VCC POR and PCI
RESET
REGISTER
Table 25.4 Chip-Level (Global) Configuration Registers (continued)
0x20 R
ADDRESS
0x22 R/W
0x23 R/W
0x24 R/W
0x21 R
0x26
0x27
A read only register which provides device identification.
A read only register which provides device revision information.
Bits[7:0] = current revision when read.
Bit[0] FDC Power
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6] Reserved
Bit[7] Reserved
0: Power Off or Disabled
1: Power On or Enabled
Reserved. This is a read/write register. Writing to this register
may cause unwanted results.
Bit[0] Reserved
Bit [1] PLL Control
= 0 PLL is on (backward Compatible)
= 1 PLL is off
Bits[3:2] OSC
= 01 Osc is on, BRG clock is on.
= 10 Same as above (01) case.
= 00 Osc is on, BRG Clock Enabled.
= 11 Osc is off, BRG clock is disabled.
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0 12-Bit Address Qualification
= 1 16-Bit Address Qualification
Note: For normal operation, bit 6 should be set.
Bit[7] Reserved
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
(Note
Bit[7:0] Configuration Address Bits [15:8]
(Note
DATASHEET
25.3)
25.3)
277
DESCRIPTION
Rev 0.2 (09-28-04)
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