SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 340

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
PWR_REC
Power Recovery
Register
Default = 0xxxxx11b
Default =x00000xxb
on a Vbat POR
Default = 0xxxxxxxb
on a VCC POR and
PCI Reset
Note: x indicates
that the bit is not
effected by this
reset condition.
SCH3112 AND
SCH3114 DEVICES
ONLY.
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
49
R/W when
bit[7] =0
(default),
except for
bit[4]
Bit[4] is a
Read-Only
bit.
Read-Only
when
bit[7]=1
OFFSET
(HEX)
REG
SCH3112 AND SCH3114 DEVICES
A/C Power Control/Recovery Register
Bit[0] Power Button Enable
0=disabled
1=enabled (default)
Bit[1] Keyboard Power Button Enable
0=disabled
1=enabled (default)
Bit[2] Power Failure Recovery Enable
0=disabled (default)
1=enabled
Bit[3] PS_ON# sampling enable
0=Sampling is disabled (Mode 1)
1=Sampling is enabled (Mode 2)
When sampling is enabled the PS_ON# pin is sampled every 0.5 seconds
and stored in an 8-bit shift register for up to a maximum of 4 seconds.
Bit[4] Previous State Bit (This read-only bit is powered by Vbat)
(NOTE: THIS BIT IS NOT RESET ON A VTR POR)
This bit contains the state of the PS_ON# pin when VTR power is removed
from the device.
0=off (PS_ON# signal was high)
1=on (PS_ON# signal was low)
Bit[6:5] APF (After Power Failure) (These bits are powered by Vbat)
(NOTE: THIS BIT IS NOT RESET ON A VTR POR)
When VTR transitions from the OFF state to the ON state, the power
recovery logic will look at the APF bits to determine if the power supply
should be off or on. If the logic determines that the Power Supply should
be place in the ON state it will generate a pulse on the PB_OUT# pin. The
auto recovery logic does not directly control the PS_ON# pin. The
PS_ON# pin is controlled by the SLP_Sx# pin.
00=Power Supply Off
01=Power Supply On
10=Power Supply set to Previous State
11=Power Supply Off
Bit[7] Register Recovery R/W Control
This bit is used to control write access to the Power Recovery Register at
offset 49h.
0=Read/Write
1=Read-OnlyA/C Power Control/Recovery Register
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
324
DESCRIPTION
SMSC SCH311X
Datasheet