SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 42

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
4.4.1
minimum potential at least 10 ms before Vcc begins a power-on cycle. Note that under all
circumstances, the hardware monitoring HVTR must be driven as the same source as VTR.
Trickle Power Functionality
When the SCH311X is running under VTR only (VCC removed), PME wakeup events are active and
(if enabled) able to assert the nIO_PME pin active low. (See PME_STS1.)
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
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The GPIOs that are used for PME wakeup as input are GP21-GP22, GP27, GP32, GP33, GP50-GP57,
GP60, GP61 (See PME_STS1.)These GPIOs function as follows (with the exception of GP60 and
GP61 - see below):
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All GPIOs listed above are PME wakeup as a GPIO (or alternate function).
GP32 and GP33 revert to their non-inverting GPIO input function when VCC is removed from the part.
The other GPIOs function as follows:
GP36, GP37 and GP40:
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GP42, GP60 and GP61:
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The following list summarizes the blocks, registers and pins that are powered by VTR.
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I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0),
these pins may only be configured as inputs. These pins have input buffers into the wakeup logic
that are powered by VTR.
I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0),
are powered by VTR. This means, at a minimum, they will source their specified current from VTR
even when VCC is present.
Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not
impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs
under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.
Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do
not have input buffers into the wakeup logic that are powered by VTR, and are not used for
wakeup.
Buffers powered by VTR. GP42 are the nIO_PME pin which is active under VTR. GP60 and GP61
have LED as the alternate function and the logic is able to control the pin under VTR.
PME interface block
PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)
Digital logic in the Hardware Monitoring block
“Wake on Specific Key” logic
LED control logic
Watchdog Timer
Power Recovery Logic
Pins for PME Wakeup:
GP42/nIO_PME (output, buffer powered by VTR)
CLOCKI32 (input, buffer powered by VTR)
nRI1 (input)
GP50/nRI2 (input)
GP52/RXD2(IRRX) (input)
KDAT/GP21 (input)
MDAT/GP32 (input)
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
26
SMSC SCH311X
Datasheet