SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 245

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
24.1
Addr
DCh-
D7h-
Reg
DAh
DBh
DFh
EAh
EBh
ECh
EDh
EEh
D6h
E0h
E8h
E9h
FFh
E1-
/Write
Read
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted
Note 24.1 The PWMx Current Duty Cycle Registers are only writable when the associated fan is in
Note 24.2 The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The
Note 24.3 The Interrupt status register bits are cleared on a write of 1 if the corresponding event is
Note 24.4 The INTEN bit in register 7Ch is always writable, both when the start bit is set and when
Note 24.5 These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the
Note 24.6 SMSC bits may be read/write bits. Writing these bits to a value other than the default value
Note 24.7 This register is reset to its default value when the PWRGD_PS signal transitions high.
Note 24.8 This bit is reset to its default value when the PWRGD_PS signal transitions high.
Note 24.9 This register always reflects the state of the pin, unless it is in spinup. During spinup this
The registers shown in the table above are the defined registers in the part. Any reads to undefined
registers always return 00h. Writes to undefined registers have no effect and do not return an error.
Undefined Registers
Enable LSbs for AutoFan
SMSC Test Register
SMSC Reserved
SMSC Reserved
SMSC Reserved
SMSC Reserved
SMSC Reserved
SMSC Reserved
PWM2 Max
PWM3 Max
Reg Name
Reserved
Reserved
Reserved
results.
manual mode. In this case, the register is writable when the start bit is set, but not when
the lock bit is set.
OVRID bit is always writable when the lock bit is set.
not active.
the lock bit is set.
hardware.
may cause unwanted results
register is forced to 00h.
Table 24.1 Register Summary (continued)
MSb
TST7
Bit 7
RES
RES
RES
RES
RES
7
7
7
7
7
7
7
DATASHEET
TST 6
Bit 6
RES
RES
RES
RES
RES
6
6
6
6
6
6
6
229
PWM3_
TST 5
Bit 5
RES
RES
RES
RES
n1
5
5
5
5
5
5
5
PWM3_
TST 4
Bit 4
RES
RES
RES
RES
n0
4
4
4
4
4
4
4
PWM2_
TST3
Bit 3
RES
RES
RES
RES
n1
3
3
3
3
3
3
3
PWM2_
TST2
Bit 2
RES
RES
RES
RES
n0
2
2
2
2
2
2
2
PWM1_
TST1
Bit 1
RES
RES
RES
RES
n1
1
1
1
1
1
1
1
PWM1_
TST0
Bit 0
LSb
RES
RES
RES
RES
n0
0
0
0
0
0
0
0
Default
Value
FFh
00h
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
N/A
Rev 0.2 (09-28-04)
Lock
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No