SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 189

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
20.3.1
APF[1:0]
00
11
01
10
10
■
If a power failure occurs and the Power Supply should be in the ON state, the Power Failure Recovery
logic will assert the PB_OUT# pin active low for a minimum pulse width of 0.5sec when VTR powers
on. If the Power Supply should remain off, the Power Failure Recovery logic will have no effect on
the PB_OUT# pin. The following table defines the possible states of PB_OUT# after a power failure
for each configuration of the APF bits.
Note: It is a requirement that the AFTERG3 bit located in the ICH controller be programmed to 1 for
PB_OUT# and PS_ON#
The PB_OUT# and PS_ON# signals are used to control the state of the power supply.
The PB_OUT# signal will be asserted low if the PB_IN# is asserted and enabled, if the KB_IN# is
asserted and enabled, or if recovering from a power failure and the power supply should be turned on.
Refer to
1. If the PB_IN# signal is enabled and asserted low, the PB_OUT# signal should be held low for as
2. If the internal KB_PB_STS# signal (see Figure 14) is asserted low, the PB_OUT# signal is held
3. If returning from a power failure and the power supply need to be turned on, a minimum of a
The PS_ON# signal is the inverse of the SLP_Sx# input signal. This signal goes directly to the Power
Supply to turn the supply on or off.
The SCH#11X indirectly controls the PS_ON# signal by asserting the PB_OUT#. PB_OUT# will be
interpreted by an external device (i.e., ICH controller), which will use this information to control the
SLP_Sx# signal.
Note: Two modes have been added to save the state of the PS_ON# pin in the event of a power
not be used by hardware, but may be read by software to determine the state of the PS_ON# pin
when the power failure occurred.
The time selected for the PS_ON# Previous State bits should be greater than or equal to the time
it takes for Resume Reset to go inactive to the time VTR is less than ~2.2 Volts.
long as the PB_IN# signal is held low.
low for as long as the KB_PB_STS# signal is held low.
~0.5sec pulse is asserted on the PB_OUT# pin. Note: This pulse width is less than 4 seconds,
since a 4 second pulse width signifies a power button override event.
DEFINITION OF APF BITS
Power Supply OFF
Power Supply ON
Power Supply set to Previous
State (ON)
Power Supply set to Previous
State (OFF)
this AC Recovery logic to be used.
failure. This allows the system to recover from a power failure. See
Failure Recovery Control (SCH3112 and SCH3114 Devices only)," on page
Figure
20.1. The following is a summary of these signals:
Table 20.3 Definition of APF Bits
DATASHEET
AFTERG3 BIT
(LOCATED IN ICH)
1
1
1
1
173
PB_OUT#
––––
––––
Section 20.3, "A/C Power
172.
Rev 0.2 (09-28-04)