SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 381

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
APPLICATION NOTE: The 5 Volt Standby power supply must power up before or simultaneous with VTR, and must
SMSC SCH311X
29.10
NAME
t1
t2
t3
V
TRIP
VTR (3.3V)
nRSMRST
DESCRIPTION
tRESET_DELAY: VTR active to nRSMRST
inactive
tRESET_FALL: VTR inactive to nRSMRST
active (Glitch width allowance)
tRESET_RISE
VTR low trip voltage
nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset
signal for the ICH.
SCH311X detects when VTR voltage raises above VTRIP, provides a delay before generating the
rising edge of nRSMRST. See definition of
This delay, tRESET_DELAY,
the
following glitch protection behavior is implemented:. When the VTR voltage rises above VTRIP,
nRSMRST will remain asserted the full tRESET_DELAY after which nRSMRST is deasserted.
On the falling edge there is minimal delay, tRESET_FALL.
Timing and voltage parameters are shown in
Resume Reset Signal Generation
VTRIP
power down simultaneous with or after VTR (from ICH2 data sheet.) SCH311X does not
have a 5 Volt Standby power supply input and does not respond to incorrect 5 Volt Standby
power - VTR sequencing.
Min
trip point. If the VTR voltage falls below
Vtrip
Max
Figure 29.27 Resume Reset Sequence
Table 29.1 Resume Reset Timing
t1
(t1 on page
DATASHEET
365) is nominally 32ms, starts when VTR voltage rises above
t3
365
VTRIP on page
MIN
140
2.7
Figure 29.27
VTRIP
TYP
350
2.8
and
365.
the during tRESET_DELAY then the
Table
t2
MAX
560
100
100
2.9
29.1.
UNITS
msec
nsec
nsec
V
Rev 0.2 (09-28-04)
NOTES