SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 106

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

REGISTER
ADDRESS
(Note
ADDR = 0
ADDR = 0
ADDR = 1
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
DLAB = 0
DLAB = 0
DLAB = 0
8.4)
Interrupt Ident. Register
MODEM Control Regis-
Interrupt Enable Regis-
Receive Buffer Regis-
FIFO Control Register
Line Control Register
Line Status Register
Transmitter Holding
REGISTER NAME
(Read Only)
(Write Only)
(Read Only)
(Write Only)
Register
ter
ter
ter
REGISTER
(Note
SYMBOL
MCR
RBR
THR
FCR
LCR
LSR
IER
Table 8.7 Register Summary for an Individual UART Channel
IIR
8.11)
RCVR Trig-
Access Bit
Data Bit 7
(Note
(Note
Data Bit 7
ger MSB
Enabled
(DLAB)
Error in
Divisor
FIFOs
RCVR
BIT 7
Latch
FIFO
0
0
8.9)
8.9)
RCVR Trig-
(Note
Data Bit 6
Data Bit 6
Set Break
ter Empty
Transmit-
Enabled
(Note 6)
ger LSB
(TEMT)
FIFOs
BIT 6
0
0
8.6)
Stick Parity
ter Holding
Data Bit 5
Data Bit 5
Reserved
Transmit-
Register
(THRE)
BIT 5
0
0
0
Break Inter-
Even Par-
Data Bit 4
Data Bit 4
Reserved
ity Select
rupt (BI)
(EPS)
BIT 4
Loop
0
0
Interrupt ID
DMA Mode
(Note
Data Bit 3
Data Bit 3
(Note
(Note
Error (FE)
MODEM
Interrupt
Framing
Enable
(EMSI)
Enable
Status
Select
(PEN)
OUT2
BIT 3
Parity
Bit
8.10)
8.9)
8.7)
Interrupt ID
Parity Error
Line Status
XMIT FIFO
Number of
Data Bit 2
(Note
Data Bit 2
Receiver
Stop Bits
Interrupt
Enable
(ELSI)
OUT1
Reset
(STB)
BIT 2
(PE)
Bit
8.7)
Send (RTS)
FIFO Reset
Select Bit 1
ter Holding
Interrupt ID
Request to
Error (OE)
Data Bit 1
Data Bit 1
(ETHREI)
Transmit-
Register
Interrupt
Overrun
(WLS1)
Enable
Length
Empty
RCVR
BIT 1
Word
Bit
Data Termi-
Data Ready
Select Bit 0
Data Avail-
“0” if Inter-
rupt Pend-
Data Bit 0
(Note
Data Bit 0
able Inter-
nal Ready
Received
(ERDAI)
(WLS0)
Enable
Enable
Length
(DTR)
BIT 0
FIFO
Word
(DR)
rupt
ing
8.5)