SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 131

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
R/W
000:
001:
010:
011:
100:
101:
110:
111:
MODE
Standard Parallel Port Mode. In this mode the FIFO is reset and common drain drivers are used on the
control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output
drivers in this mode.
PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines
and reading the data register returns the value on the data lines and not the value in the data register.
All drivers have active pull-ups (push-pull).
Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO.
FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is
only useful when direction is 0. All drivers have active pull-ups (push-pull).
ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes
written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using
ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and
packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull).
Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in
configuration register L3-CRF0. All drivers have active pull-ups (push-pull).
Reserved
Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the
parallel port.
Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All
drivers have active pull-ups (push-pull).
0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has
case dmaEn=1:
case dmaEn=0 direction=0:
case dmaEn=0 direction=1:
the FIFO.
Bit 1 full
Read only
1: The FIFO cannot accept another byte or the FIFO is completely full.
0: The FIFO has at least 1 free byte.
Bit 0 empty
Read only
1: The FIFO is completely empty.
0: The FIFO contains at least 1 byte of data.
occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the
interrupts. Writing this bit to a 1 will not cause an interrupt.
This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from
During DMA (this bit is set to a 1 when terminal count is reached).
This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO.
All drivers have active pull-ups (push-pull).
Table 9.6 Extended Control Register (a)
DATASHEET
115
Rev 0.2 (09-28-04)