SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 36

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
105
106
107
PIN
NOTE
2.9
2.9
2.9
Note: The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates
Note 2.1
Note 2.2
Note 2.3
Note 2.4
Note 2.5
Note 2.6
Note 2.7
Note 2.8
Note 2.9
Note 2.10 This analog input is backdrive protected. Although HVTR is powered by VTR, it is
Note 2.11 The GP53/TXD2(IRTX) pin defaults to the GPIO input function on a VTR POR and
Note 2.12 These pins are multiplexed internally with the FDC I/F. When the FDC on PP mode is
GP67* /
nRTS4
GP62* /
nCTS4
GP34 /
nDTR4
an “Active Low” signal.
NAME
Table 2.7 SCH3116 Specific Signals (
Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in
parenthesis represent multiple buffer types for a single pin function.
Pins that have input buffers must always be held to either a logical low or a logical high
state when powered. Bi-directional buses that may be trisected should have either weak
external pull-ups or pull-downs to hold the pins in a logic state (i.e., logic states are VCC
or ground).
VCC and VSS pins are for Super I/O Blocks. HVTR and HVSS are dedicated for the
Hardware Monitoring Block.
VTR can be connected to VCC if no wake-up functionality is required.
The Over Current Sense Pin requires an external pull-up (30ua pull-up is suggested).
External pull-ups must be placed on the nKBDRST and A20M pins. These pins are GPIOs
that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions
are to be used, the system must ensure that these pins are high.
The nRTS1/SYSOPT0 pin requires an external pull-down resistor to put the base I/O
address for configuration at 0x02E.
base I/O address for configuration to 0x04E.
The LED pins are powered by VTR so that the LEDs can be controlled when the part is
under VTR power.
This pin is an input into the wake-up logic that is powered by VTR. In the case of a ring
indicator for a serial port, or a GPIO it will also go to VCC powered logic. This logic must
be disabled when VCC=0.
possible that monitored power supplies may be powered when HVTR is off.
presents a tristate impedance. When VCC=0 the pin is tristate. If GP53 function is
selected and VCC is power is applied, the pin reflects the current state of GP53. The
GP53/TXD2(IRTX) pin is tristate when it is configured for the TXD2 (IRTX) function under
various conditions detailed in
selected, the PP port alternate functions are used for the FDC I/F.
GPIO with I_VID buffer
Input /
Request to Send 4
GPIO with I_VID buffer
Input /
Clear to Send 4
GPIO /
Data Terminal Ready 4
DESCRIPTION
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Section 8.1.1, "IR Transmit Pin," on page 93
20
nRTS4
nCTS4
nDTR4
An external pull-up resistor is required to move the
POWER
PLANE
VCC
Note
2.15)
GP67*
GP62*
GP34
(continued)
POWER
PLANE
VTR-
NO GATE
(Note 2.1
OPERA-
VCC=0
TION
HI-Z
HI-Z
6)
/
/
SMSC SCH311X
OP14 /
I
I
O6
(Note
BUFFER
MODES
.
Datasheet
2.1)