SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 285

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 25 Config Registers
APPLICATION NOTE: The nRTS1/SYSOPT0 and the nDTR1/SYSOPT1 pins requires external pullup/pulldown
SMSC SCH311X
SYSOPT1
1
1
0
0
The Configuration of the SCH311X is very flexible and is based on the configuration architecture
implemented in typical Plug-and-Play components. The SCH311X is designed for motherboard
applications in which the resources required by their components are known. With its flexible resource
allocation architecture, the SCH311X allows the BIOS to assign resources at POST.
SYSTEM ELEMENTS
Primary Configuration Address Decoder
After a PCI Reset or Vcc Power On Reset the SCH311X is in the Run Mode with all logical devices
disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX
and DATA) by placing the SCH311X into Configuration Mode.
The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and
DATA ports are only valid when the SCH311X Is in Configuration Mode.
Strap options must be added to allow four Configuration Register Base Address options: 0x002E,
0x004E, 0x162E, or 0x164E.
nRTS1/SYSOPT0
■
■
At the deasertting edge of PCIRST# or VCC POR the
determine the configuration base address:
■
■
The above strap options will allow the Configuration Access Ports (CONFIG PORT, the INDEX PORT,
and DATA PORT) to be controlled by the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins and by the
Configuration Port Base Address registers at offset 0x26 and 0x27. The configuration base address at
power-up is determined by the SYSOPT strap option. The SYSOPT strap option is latched state of
the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins at the deasserting edge of PCIRST#. The
nRTS1/SYSOPT0 pin determines the lower byte of the Base Address and the nDTR1/SYSOPT1 pin
determines the upper byte of the Base Address. The following table summarizes the Base
Configuration address selected by the SYSOPT strap option.
Note: An external pull-down resistor is required for the base IO address to be 0x02E for configuration.
The INDEX and DATA ports are effective only when the chip is in the Configuration State.
0 = Index Base I/O Address bits A[7:0]= 0x2E
1 = Index Base I/O Address bits A[7:0]= 0x4E
0 = Index Base I/O Address bits A[15:8]= 0x16;
1 = Index Base I/O Address bits A[15:8]= 0x00
SYSOPT0
0
1
0
1
Table 25.1 SYSOPT Strap Option Configuration Address Select
An external pull-up resistor is required to move the base IO address for configuration to 0x04E.
resistors to set the default base I/O address for configuration to 0x002E, 0x004E, 0x162E,
or 0x164E.
pin is latched to determine the configuration base address:
DEFAULT CONFIG PORT/
INDEX PORT ADDRESS
0x002E
0x004E
0x162E
0x164E
At the deasertting edge of PCIRST# or VCC POR the
DATASHEET
269
nDTR1/SYSOPT1
DATA PORT
INDEX PORT + 1
pin is latched to
Rev 0.2 (09-28-04)