SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 208

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
23.8.1
Interrupt Enable Bits
Each interrupt event can be enabled into the interrupt status registers. See the figure below for the
status and enable bits used to control the interrupt bits and nHWM_INT pin. Note that a status bit will
not be set if the individual enable bit is not set.
The following is a list of the Interrupt Enable registers:
■
■
Note: Clearing the individual enable bits will clear the corresponding individual status bit.
Clearing the individual enable bits. There are two cases and in both cases it is not possible to change
the individual interrupt enable while the start bit is set.
1. The interrupt status bit will never be set when the individual interrupt enable is cleared. Here the
2. If an interrupt status bit had been set from a previous condition, clearing the start bit and then
Interrupt Enable Register - Fan Tachs (80h)
Interrupt Enable Register - Temp (82h)
interrupt status bit will not get set when the start bit is set, regardless of whether the limits are
violated during a measurement.
clearing the individual interrupt enable bit will not clear the associated interrupts status bit
immediately. It will be cleared when the start bit is set, when the associated reading register is
updated.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
192
SMSC SCH311X
Datasheet