SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 47

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 6 LPC Interface
SMSC SCH311X
6.1
6.1.1
6.1.2
6.2
LAD[3:0]
LFRAME#
PCI_RESET#
PCI_CLK
LDRQ#
SER_IRQ
CLKRUN#
nIO_PME
LPCPD#
LSMI#
SIGNAL
SIGNAL
NAME
NAME
Memory Read
CYCLE TYPE
Memory Write
I/O Read
I/O Write
The signals implemented for the LPC bus interface are described in the tables below. LPC bus signals
use PCI 33MHz electrical signal characteristics.
LPC Required Signals
LPC Optional Signals
Table 6.1
ignored.
LPC Interface Signal Definition
Supported LPC Cycles
I/O
Input
Input
Input
Output
I/O
OD
OD
I
OD
TYPE
TYPE
summarizes the cycle types are supported by the SCH311X. All other cycle types are
PCI Reset. Used as LPC Interface Reset. Same functionality as RST_DRV but active
PCI Clock.
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken cycle
low 3.3V.
Encoded DMA/Bus Master request for the LPC interface.
Serial IRQ.
Clock Run
Same as the PME# or Power Mgt Event signal. Allows the
SCH311X to request wakeup in S3 and below.
Power down - Indicates that the device should prepare for
LPC I/F shutdown
Only need for SMI# generation on I/O instruction for retry.
Table 6.1 Supported LPC Cycles
TRANSFER SIZE
DATASHEET
1 Byte
1 Byte
1 Byte
1 Byte
DESCRIPTION
31
DESCRIPTION
Not Supported
Not Supported
COMMENT
Supported
Supported
Implemented
Implemented
Not Implemented
Implemented
Not Implemented
Not Implemented
COMMENT
Rev 0.2 (09-28-04)