AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 91

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Status Stage
Control Transactions
Setup Stage
Data Stage: Control Endpoint
Direction
4109E–8051–06/03
The DIR bit in the UEPSTAX register should be at 0.
Receiving Setup packets is the same as receiving Bulk Out packets, except that the
RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the
RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the
Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEP-
STAX register are cleared and an interrupt is triggered if enabled.
The firmware has to read the Setup request stored in the Control endpoint FIFO before
clearing the RXSETUP bit to free the endpoint FIFO for the next transaction.
The data stage management is similar to Bulk management.
A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and
OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The
firmware has to specify the control endpoint direction for the data stage using the DIR bit
in the UEPSTAX register.
•
•
To send a STALL handshake, see “STALL Handshake” on page 94.
The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage.
The status stage management is similar to Bulk management.
•
•
If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX
register before writing into the FIFO and sending the data by setting to 1 the TXRDY
bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has
been set by the hardware. The firmware should clear the TXCMPL bit before any
other transaction.
If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The
RXOUTB0 bit is set by hardware when a new valid packet has been received on the
endpoint. The firmware must read the data stored into the FIFO and then clear the
RXOUTB0 bit to reset the FIFO and to allow the next transaction.
For a Control Write transaction or a No-Data Control transaction, the status stage
consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in
Standard Mode” on page 89). To send a STALL handshake, see “STALL
Handshake” on page 94.
For a Control Read transaction, the status stage consists of a OUT Zero Length
Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 87).
AT8xC51SND1C
91