AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 119

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Data Transmitter
Configuration
Data Loading
Data Transmission
End of Transmission
Busy Status
4109E–8051–06/03
Figure 84. Data Controller Configuration Flows
For transmitting data to the card user must first configure the data controller in transmis-
sion mode by setting the DATDIR bit in MMCON1 register.
Figure 85 summarizes the data stream transmission flows in both polling and interrupt
modes while Figure 86 summarizes the data block transmission flows in both polling
and interrupt modes, these flows assume that block length is greater than 16 data.
Data is loaded in the FIFO by writing to MMDAT register. Number of data loaded may
vary from 1 to 16 Bytes. Then if necessary (more than 16 Bytes to send) user must wait
that one FIFO becomes empty (F1EI or F2EI set) before loading 8 new data.
Transmission is enabled by setting and clearing DATEN bit in MMCON1 register.
Data is transmitted immediately if the response has already been received, or is delayed
after the response reception if its status is correct. In both cases transmission is delayed
if a card sends a busy state on the data line until the end of this busy condition.
According to the MMC specification, the data transfer from the host to the card may not
start sooner than 2 MMC clock periods after the card response was received (formally
N
DATD1:0 bits in MMCON2 register from 3 MMC clock periods when DATD1:0 bits are
cleared to 9 MMC clock periods when DATD1:0 bits are set, by step of 2 MMC clock
periods.
The end of a data frame (block or stream) transmission is signalled to you by the EOFI
flag in MMINT register. This flag may generate an MMC interrupt request as detailed in
Section "Interrupt", page 124.
In data stream mode, EOFI flag is set, after reception of the End bit. This assumes user
has previously sent the STOP command to the card, which is the only way to stop
stream transfer.
In data block mode, EOFI flag is set, after reception of the CRC status token (see
Figure 76). 2 other flags in MMSTA register: DATFS and CRC16S report a status on the
frame sent. DATFS indicates if the CRC status token format is correct or not, and
CRC16S indicates if the card has found the CRC16 of the block correct or not.
As shown in Figure 76 the card uses a busy token during a block write operation. This
busy status is reported to you by the CBUSY flag in MMSTA register and by the MCBI
flag in MMINT which is set every time CBUSY toggles, i.e. when the card enters and
exits its busy state. This flag may generate an MMC interrupt request as detailed in Sec-
tion "Interrupt", page 124.
WR
parameter). To address all card types, this delay can be programmed using
Configure Format
Configuration
Data Stream
DFMT = 0
Data Single Block
Configure Format
BLEN3:0 = XXXXb
Configuration
MBLOCK = 0
DFMT = 1
AT8xC51SND1C
Data Multi-Block
Configure Format
BLEN3:0 = XXXXb
Configuration
MBLOCK = 1
DFMT = 1
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