AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 60

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Watchdog Operation
WDT Behavior during Idle and
Power-down Modes
60
AT8xC51SND1C
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and
E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip
reset to disable it. If it is not cleared using the previous sequence, the WDT overflows
and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse
on the RST pin to globally reset the application (refer to Section “Power Management”,
page 46).
The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG
register accordingly to the formula shown in Figure 40. In this formula, WTOval repre-
sents the decimal value of WTO2:0 bits. Table 66 reports the time-out period depending
on the WDT frequency.
Figure 40. WDT Time-Out Formula
Table 66. WDT Time-Out Computation
Notes:
Operation of the WDT during power reduction modes deserves special attention.
The WDT continues to count while the AT8xC51SND1C is in Idle mode. This means
that you must dedicate some internal or external hardware to service the WDT during
Idle mode. One approach is to use a peripheral Timer to generate an interrupt request
when the Timer overflows. The interrupt service routine then clears the WDT, reloads
the peripheral Timer for the next service period and puts the AT8xC51SND1C back into
Idle mode.
The Power-down mode stops all phase clocks. This causes the WDT to stop counting
and to hold its count. The WDT resumes counting from where it left off if the Power-
down mode is terminated by INT0, INT1 or keyboard interrupt. To ensure that the WDT
does not overflow shortly after exiting the Power-down mode, it is recommended to clear
the WDT just before entering Power-down mode.
The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
WTO2 WTO1 WTO0
0
0
0
0
1
1
1
1
1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:
2. These frequencies are achieved in X2 mode when WTX2 = 0: F
0
0
1
1
0
0
1
1
F
WDT
= F
0
1
0
1
0
1
0
1
WDT
OSC
6 MHz
÷ 2.
TO
131.07
262.14
524.29
16.38
32.77
65.54
1049
2097
=
(1)
6
⋅ ((
2
8 MHz
14
196.56
786.24
12.28
24.57
49.14
98.28
393.1
1572
F
⋅
WDT
2
WTOval
(1)
) – 1)
10 MHz
157.29
314.57
629.15
19.66
39.32
78.64
1258
9.83
F
(1)
WDT
(ms)
12 MHz
131.07
262.14
524.29
16.38
32.77
65.54
1049
8.19
(2)
16 MHz
196.56
393.12
786.24
WDT
12.28
24.57
49.14
98.28
6.14
= F
(2)
4109E–8051–06/03
OSC
20 MHz
.
157.29
314.57
629.15
19.66
39.32
78.64
4.92
9.83
(2)