AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 177

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Registers
4109E–8051–06/03
Table 147. ADCON Register
ADCON (S:F3h) – ADC Control Register
Reset Value = 0000 0000b
Table 148. ADCLK Register
ADCLK (S:F2h) – ADC Clock Divider Register
Reset Value = 0000 0000b
Number
Number
2 - 1
7 - 5
4 - 0
Bit
Bit
7
7
-
-
7
6
5
4
3
0
Mnemonic Description
Mnemonic Description
ADCD4:0
ADIDL
ADEOC
ADSST
ADIDL
ADEN
ADCS
Bit
Bit
6
6
-
-
-
-
Reserved
The value read from this bit is always 0. Do not set this bit.
ADC Pseudo-Idle Mode
Set to suspend the CPU core activity (pseudo-idle mode) during conversion.
Clear by hardware at the end of conversion.
ADC Enable Bit
Set to enable the A to D converter.
Clear to disable the A to D converter and put it in low power stand by mode.
End Of Conversion Flag
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
Start and Status Bit
Set to start an A to D conversion on the selected channel.
Cleared by hardware at the end of conversion.
Reserved
The value read from these bits is always 0. Do not set these bits.
Channel Selection Bit
Set to select channel 0 for conversion.
Clear to select channel 1 for conversion.
Reserved
The value read from these bits is always 0. Do not set these bits.
ADC Clock Divider
5-bit divider for ADC clock generation.
ADEN
5
5
-
ADEOC
ADCD4
4
4
ADSST
ADCD3
3
3
AT8xC51SND1C
ADCD2
2
2
-
ADCD1
1
1
-
ADCD0
ADCS
0
0
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