AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 175

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Clock Generator
Channel Selection
Conversion Precision
Configuration
4109E–8051–06/03
The ADC clock is generated by division of the peripheral clock (see details in
section “X2 Feature”, page 12). The division factor is then given by ADCP4:0 bits in
ADCLK register. Figure 131 shows the ADC clock generator and its calculation
formula
Figure 131. ADC Clock Generator and Symbol Caution:
Note:
The channel on which conversion is performed is selected by the ADCS bit in ADCON
register according to Table 146.
Table 146. ADC Channel Selection
The 10-bit precision conversion is achieved by stopping the CPU core activity during
conversion for limiting the digital noise induced by the core. This mode called the
Pseudo-Idle mode
when conversion is launched (see Section "Conversion Launching", page 176), the
CPU core is stopped until the end of the conversion (see Section "End Of Conversion",
page 176). This bit is cleared by hardware at the end of the conversion.
Notes:
The ADC configuration consists in programming the ADC clock as detailed in the Sec-
tion "Clock Generator", page 175. The ADC is enabled using the ADEN bit in ADCON
register. As shown in Figure 93, user must wait the setup time (T
any conversion.
CLOCK
PER
(1)
1. In all cases, the ADC clock frequency may be higher than the maximum F
2. The ADCD value of 0 is equivalent to an ADCD value of 32.
1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle
2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and pro-
3. Concurrently with ADSST bit.
.
parameter reported in the section “Analog to Digital Converter”, page 197.
mode.
cessed, according to their priority after the end of the conversion.
÷ 2
(1),(2)
ADCS
0
1
is enabled by setting the ADIDL bit in ADCON register
ADCD4:0
ADCLK
ADCclk
=
-------------------------
2 ADCD
PERclk
⋅
ADC Clock
AT8xC51SND1C
Channel
AIN1
AIN0
SETUP
ADC Clock Symbol
) before launching
CLOCK
ADC
(3)
. Thus,
ADCLK
175