AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 113

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Data Packet Format
Clock Control
4109E–8051–06/03
Table 108. R3 Response Format (OCR Register)
Table 109. R4 Response Format (Fast I/O)
Table 110. R5 Response Format
There are 2 types of data packets: stream and block. As shown in Figure 77, stream
data packets have an indeterminate length while block packets have a fixed length
depending on the block length. Each data packet is preceded by a Start bit: a low level
on MCMD line and succeeded by an End bit: a high level on MCMD line. Due to the fact
that there is no predefined end in stream packets, CRC protection is not included in this
case. The CRC protection algorithm for block data is a 16-bit CCITT polynomial.
Figure 77. Data Token Format
The MMC bus clock signal can be used by the host to turn the cards into energy saving
mode or to control the data flow (to avoid under-run or over-run conditions) on the bus.
The host is allowed to lower the clock frequency or shut it down.
There are a few restrictions the host must follow:
•
•
Bit Position
Description
Width (bits)
Bit Position
Description
Width (bits)
Bit Position
Width (bits)
Description
Value
Value
Value
The bus frequency can be changed at any time (under the restrictions of maximum
data transfer frequency, defined by the cards, and the identification frequency
defined by the specification document).
It is an obvious requirement that the clock must be running for the card to output
data or response tokens. After the last MultiMedia Card bus transaction, the host is
Sequential Data
Block Data
Start bit
Start bit
Start bit
47
47
‘0’
47
‘0’
1
‘0’
1
1
Transmission
Transmission
0
0
Transmission
46
46
bit
‘0’
‘0’
bit
46
1
1
‘0’
bit
1
Command
Reserved
Command
‘101000’
[45:40]
[45:40]
‘111111’
[45:40]
‘100111’
Index
Index
Block Length
6
6
6
Content
Content
Argument
Argument
register
[39:8]
[39:8]
[39:8]
OCR
32
32
32
AT8xC51SND1C
-
-
-
Reserved
‘1111111’
CRC7
CRC7
[7:1]
[7:1]
[7:1]
7
7
7
-
-
CRC
1
1
End bit
End bit
End bit
0
‘1’
0
‘1’
0
‘1’
1
1
1
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