AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet
AT83C51SND1C_03
Related parts for AT83C51SND1C_03
AT83C51SND1C_03 Summary of contents
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Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control using 31 Steps) – Bass, Medium, and ...
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Typical Applications Block Diagram Figure 1. AT8xC51SND1C Block Diagram INT0 INT1 VDD VSS UVDD 3 3 Interrupt Handler Unit RAM 2304 Bytes C51 (X2 Core) MP3 Decoder Clock and PLL Unit FILT X1 X2 RST ISP 1 Alternate function of ...
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Pin Description Pinouts 4109E–8051–06/03 Figure 2. AT89C51SND1C 80-pin QFP Package ALE 1 (1) ISP/NC 2 P1.0/KIN0 3 P1.1/KIN1 4 P1.2/KIN2 5 P1.3/KIN3 6 P1.4 7 P1.5 8 P1.6/SCL 9 AT89C51SND1C-RO (FLASH) P1.7/SDA 10 AT83C51SND1C-RO (ROM) VDD 11 PVDD 12 FILT ...
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AT8xC51SND1C 4 Figure 3. AT8xC51SND1C 81-pin BGA Package P2.0/ P4.0/ P4.2/ P4.6 A8 MISO SCK P4.1/ P4.3/ P4.4 P4.7 MOSI SS P2.5/ P2.2/ P2.1/ P0.6 A13 A10 A9 P2.4/ P2.6/ P0.7/ P4.5 A12 A14 AD7 P2.3/ ...
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Figure 4. AT8xC51SND1C 84-pin PLCC Package ALE 12 ISP 13 P1.0/KIN0 14 P1.1/KIN1 15 P1.2/KIN2 16 P1.3/KIN3 17 P1.4 18 P1.5 19 P1.6/SCL 20 P1.7/SDA 21 AT89C51SND1C-SR (FLASH) VDD 22 PAVDD 23 FILT 24 PAVSS 25 VSS 26 X2 ...
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Signals AT8xC51SND1C 6 All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Signal Name Type Description Port 8-bit open-drain bidirectional I/O port. Port 0 pins that ...
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Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 ...
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AT8xC51SND1C 8 Table 6. MutiMediaCard Interface Signal Description Signal Name Type Description MMC Clock output MCLK O Data or command clock transfer. MMC Command line Bidirectional command channel used for card initialization and data MCMD I/O transfer commands. To avoid ...
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Table 10. A/D Converter Signal Description Signal Name Type Description AIN1:0 I A/D Converter Analog Inputs AREFP I Analog Positive Voltage Reference Input Analog Negative Voltage Reference Input AREFN I This pin is internally connected to AVSS. Table 11. ...
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AT8xC51SND1C 10 Table 13. System Signal Description Signal Name Type Description Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a ...
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Internal Pin Structure 4109E–8051–06/03 Table 15. Detailed Internal Pin Structure Circuit VDD Watchdog Output 2 osc periods Latch Output Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the Section “DC Characteristics”, page 181. 2. ...
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Clock Controller Oscillator X2 Feature AT8xC51SND1C 12 The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an on- chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. The ...
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PLL PLL Description 4109E–8051–06/03 Figure 7. Mode Switching Waveforms X1 X1 ÷ Bit Clock STD Mode Note order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using ...
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PLL Programming AT8xC51SND1C 14 Figure 9. PLL Filter Connection FILT The PLL is programmed using the flow shown in Figure 10. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure ...
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Registers 4109E–8051–06/03 Table 16. CKCON Register CKCON (S:8Fh) – Clock Control Register WDX2 - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Watchdog ...
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AT8xC51SND1C 16 Table 18. PLLNDIV Register PLLNDIV (S:EEh) – PLL N Divider Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this ...
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Program/Code Memory Figure 11. Program/Code Memory Organization FFFFh 64K Bytes Code ROM 0000h AT83C51SND1C ROM Memory Architecture Figure 12. AT83C51SND1C Memory Architecture 4109E–8051–06/03 The AT8xC51SND1C implement 64K Bytes of on-chip program/code memory. Figure 11 shows the split of internal and ...
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User Space Flash Memory Architecture Figure 13. AT89C51SND1C Memory Architecture FFFFh Flash Memory 0000h User Space Boot Space Hardware Security Space Extra Row Space AT8xC51SND1C 18 This space is composed of a 64K Bytes ROM memory programmed during the manu- ...
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Hardware Security System Boot Memory Execution Software Boot Mapping Hardware Condition Boot Mapping Programmed Condition Boot Mapping 4109E–8051–06/03 The AT89C51SND1C implements three lock bits LB2:0 in the LSN of HSB (see Table 22) providing three levels of security for user’s ...
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Figure 14. Hardware Boot Process Algorithm Preventing Flash Corruption AT8xC51SND1C 20 RESET Hard Cond? ISP = L? Prog Cond? BLJB = P? Standard Init Prog Cond Init ENBOOT = 0 ENBOOT = 0000h PC = F000h FCON ...
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Registers 4109E–8051–06/03 Table 21. AUXR1 Register AUXR1 (S:A2h) – Auxiliary Register ENBOOT Bit Bit Number Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these ...
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Hardware Bytes AT8xC51SND1C 22 Table 22. HSB Byte – Hardware Security Byte X2B BLJB - Bit Bit Number Mnemonic Description X2 Bit (1) 7 X2B Program this bit to start in X2 mode. Unprogram (erase) this bit ...
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Data Memory Figure 15. Internal and External Data Memory Organization 7FFh 2K Bytes Internal ERAM EXTRAM = 0 00h Internal Space Lower 128 Bytes RAM 4109E–8051–06/03 The AT8xC51SND1C provides data memory access in 2 different spaces: 1. The internal space ...
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Upper 128 Bytes RAM Expanded RAM AT8xC51SND1C 24 Figure 16. Lower 128 Bytes Internal RAM Organization 30h 20h 18h 10h 08h 00h The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. ...
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External Space Memory Interface Page Access Mode 4109E–8051–06/03 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 17 shows the structure of the external ...
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External Bus Cycles CPU Clock AT8xC51SND1C 26 This section describes the bus cycles the AT8xC51SND1C executes to read (see Figure 18), and write data (see Figure 19) in the external data memory. External memory cycle takes 6 CPU clock periods. ...
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Dual Data Pointer Description Application 4109E–8051–06/03 The AT8xC51SND1C implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as ...
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Registers AT8xC51SND1C 28 Table 28. PSW Register PSW (S:8Eh) – Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag ...
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Table 29. AUXR Register AUXR (S:8Eh) – Auxiliary Control Register EXT16 M0 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. External 16-bit ...
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Special Function Registers Table 30. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low Byte DPH 83h Data Pointer High Byte Table ...
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Table 34. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 P4 C0h 8-bit Port 4 P5 D8h 4-bit Port 5 Table 35. Flash ...
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Table 37. MP3 Decoder SFRs Mnemonic Add Name MP3CON AAh MP3 Control MP3STA C8h MP3 Status MP3STA1 AFh MP3 Status 1 MP3DAT ACh MP3 Data MP3ANC ADh MP3 Ancillary Data MP3VOL 9Eh MP3 Audio Volume Control Left MP3VOR 9Fh MP3 ...
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Table 39. USB Controller SFRs Mnemonic Add Name USBCON BCh USB Global Control USBADDR C6h USB Address USBINT BDh USB Global Interrupt USBIEN BEh USB Global Interrupt Enable UEPNUM C7h USB Endpoint Number UEPCONX D4h USB Endpoint X Control UEPSTAX ...
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Table 42. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 92h Baud Rate Control BRL 91h Baud Rate Reload Table 43. SPI ...
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Table 47. SFR Addresses and Reset Values 0/8 1/9 UEPINT DAT16H F8h 0000 0000 XXXX XXXX (1) B F0h 0000 0000 PLLCON E8h 0000 1000 (1) ACC E0h 0000 0000 (1) P5 D8h XXXX 1111 (1) (3) PSW FCON D0h ...
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Interrupt System Interrupt System Priorities AT8xC51SND1C 36 The AT8xC51SND1C, like other control-oriented computer architectures, employ a pro- gram interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution ...
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Table 49. Priority Levels IPHxx IPLxx low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. Higher priority interrupts are serviced before lower priority ...
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Figure 21. Interrupt Control System External INT0 Interrupt 0 Timer 0 External INT1 Interrupt 1 Timer 1 TXD Serial Port RXD MP3 Decoder Audio Interface MCLK MMC MDAT Controller MCMD SCL TWI Controller SDA SCK SPI SI Controller SO A ...
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External Interrupts INT1:0 Inputs KIN3:0 Inputs Input Sampling 4109E–8051–06/03 External interrupts INT0 and INT1 (INTn pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn ...
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Registers AT8xC51SND1C 40 Table 51. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register EAUD EMP3 Bit Bit Number Mnemonic Description Enable All Interrupt Bit Set to enable all interrupts. Clear to disable all interrupts. 7 ...
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Table 52. IEN1 Register IEN1 (S:B1h) – Interrupt Enable Register EUSB - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. ...
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AT8xC51SND1C 42 Table 53. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register IPHAUD IPHMP3 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...
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Table 54. IPH1 Register IPH1 (S:B3h) – Interrupt Priority High Register IPHUSB - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this ...
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AT8xC51SND1C 44 Table 55. IPL0 Register IPL0 (S:B8h) - Interrupt Priority Low Register IPLAUD IPLMP3 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...
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Table 56. IPL1 Register IPL1 (S:B2h) – Interrupt Priority Low Register IPLUSB - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this ...
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Power Management Reset Cold Reset AT8xC51SND1C 46 2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks ...
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Warm Reset Watchdog Reset Reset Recommendation to Prevent Flash Corruption Idle Mode 4109E–8051–06/03 Table 58. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor Oscillator Start-Up Time 820 2.7 µF Note: 1. ...
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Entering Idle Mode Exiting Idle Mode Power-down Mode Entering Power-down Mode Exiting Power-down Mode AT8xC51SND1C 48 To enter Idle mode, the user must set the IDL bit in PCON register (see Table 59). The AT8xC51SND1C enters Idle mode upon execution ...
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Figure 26. Power-down Exit Waveform Using INT1:0 INT1:0 OSC Active phase Figure 27. Power-down Exit Waveform Using KIN3:0 1 KIN3:0 OSC Active phase Note: 1. KIN3:0 can be high or low-level triggered. 4109E–8051–06/03 resumes when the input is released (see ...
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Registers AT8xC51SND1C 50 Table 59. PCON Register PCON (S:87h) – Power Configuration Register Bit Bit Number Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set ...
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Timers/Counters Timer/Counter Operations Timer Clock Controller 4109E–8051–06/03 The AT8xC51SND1C implement 2 general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as ...
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Figure 28. Timer 0 and Timer 1 Clock Controller and Symbols PER CLOCK OSC ÷ 2 CLOCK CKCON.1 TIM0 CLOCK Timer 0 Clock Symbol Timer 0 Mode 0 (13-bit Timer) Figure 29. Timer/Counter ...
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Mode 1 (16-bit Timer) Figure 31. Timer/Counter Mode 1 TIMx ÷ 6 CLOCK Tx C/Tx# TMOD Reg INTx GATEx TMOD Reg Figure 32. Mode 1 Overflow Period Formula Mode 2 (8-bit Timer with ...
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Figure 35. Timer/Counter 0 in Mode 3: 2 8-bit Counters TIM0 ÷ 6 CLOCK T0 C/T0# TMOD.2 INT0 GATE0 TMOD.3 TIM0 ÷ 6 CLOCK Figure 36. Mode 3 Overflow Period Formula TF0 Timer 1 AT8xC51SND1C 54 3. Figure 34 gives ...
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Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) Interrupt Figure 37. Timer Interrupt System 4109E–8051–06/03 Mode 0 configures Timer 13-bit Timer, which is set ...
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Registers AT8xC51SND1C 56 Table 60. TCON Register TCON (S:88h) – Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set ...
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Table 61. TMOD Register TMOD (S:89h) – Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. ...
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AT8xC51SND1C 58 Table 63. TL0 Register TL0 (S:8Ah) – Timer 0 Low Byte Register Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 64. TH1 Register ...
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Watchdog Timer Description Figure 38. WDT Block Diagram WDT ÷ 6 CLOCK 1Eh-E1h Decoder System Reset RST Watchdog Clock Controller Figure 39. WDT Clock Controller and Symbol PER CLOCK OSC ÷ CLOCK 4109E–8051–06/03 The AT8xC51SND1C implement a hardware Watchdog Timer ...
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Watchdog Operation WDT Behavior during Idle and Power-down Modes AT8xC51SND1C 60 After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into the WDTRST register. As soon enabled, there is ...
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Registers 4109E–8051–06/03 Table 67. WDTRST Register WDTRST (S:A6h Write only) – Watchdog Timer Reset Register Bit Bit Number Mnemonic Description Watchdog Control Value Reset Value = XXXX XXXXb Figure 41. ...
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MP3 Decoder Decoder Description Figure 42. MP3 Decoder Block Diagram 1K Bytes Audio Data 8 Frame Buffer From C51 MP3DAT MPxREQ MP3 MP3STA1.n CLOCK MPEN MP3CON.7 MPBBST MP3CON.6 AT8xC51SND1C 62 The AT8xC51SND1C implement a MPEG I/II audio layer 3 decoder ...
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MP3 Data MP3 Clock 4109E–8051–06/03 The MP3 decoder does not start any frame decoding before having a complete frame in (1) its input buffer . In order to manage the load of MP3 data in the frame buffer, a hard- ...
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Audio Controls Volume Control Equalization Control Special Effect Decoding Errors Layer Error Synchronization Error CRC Error AT8xC51SND1C 64 The MP3 decoder implements volume control on both right and left channels. The MP3VOR and MP3VOL registers allow a 32-step volume control ...
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Frame Information Ancillary Data 4109E–8051–06/03 The MP3 frame header contains information on the audio data contained in the frame. These informations is made available in the MP3STA register for you information. MPVER and MPFS1:0 bits allow decoding of the sampling ...
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Interrupt Description Management AT8xC51SND1C 66 As shown in Figure 46, the MP3 decoder implements five interrupt sources reported in ERRCRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register. All these sources are maskable separately using MSKCRC, MSKSYN, MSKLAY, MSKREQ, ...
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Figure 47. MP3 Interrupt Service Routine Flow Data Request Handler Write MP3 Data to MP3DAT Synchro Error Handler Reload MP3 Frame Through MP3DAT Note: 1. Test these bits only if needed (unmasked interrupt). AT8xC51SND1C MP3 Decoder ISR Read MP3STA ...
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Registers AT8xC51SND1C 68 Table 72. MP3CON Register MP3CON (S:AAh) – MP3 Decoder Control Register MPEN MPBBST CRCEN Bit Bit Number Mnemonic Description MP3 Decoder Enable Bit 7 MPEN Set to enable the MP3 decoder. Clear to disable ...
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Table 73. MP3STA Register MP3STA (S:C8h Read Only) – MP3 Decoder Status Register MPANC MPREQ ERRLAY Bit Bit Number Mnemonic Description Ancillary Data Available Flag 7 MPANC Set by hardware as soon as one ancillary data ...
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AT8xC51SND1C 70 Table 75. MP3STA1 Register MP3STA1 (S:AFh) – MP3 Decoder Status Register Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do ...
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Table 78. MP3VOR Register MP3VOR (S:9Fh) – MP3 Volume Right Control Register Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not ...
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AT8xC51SND1C 72 Table 81. MP3TRE Register MP3TRE (S:B6h) – MP3 Treble Control Register TRE5 Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not ...
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Audio Output Interface Description Figure 48. Audio Interface Block Diagram AUD CLOCK AUDEN AUDCON1.0 Audio Data 16 From MP3 Decoder Sample Request To MP3 Decoder Audio Data 8 From C51 4109E–8051–06/03 The AT8xC51SND1C implement an audio output interface allowing the ...
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Clock Generator Data Converter AT8xC51SND1C 74 The audio interface clock is generated by division of the PLL clock. The division factor is given by AUCD4:0 bits in CLKAUD register. Figure 49 shows the audio interface clock generator and its calculation ...
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Figure 51. Audio Output Format DSEL DCLK 1 2 DOUT LSB MSB B14 DSEL DCLK 1 2 DOUT MSB B14 DSEL DCLK 1 2 DOUT MSB B14 DSEL DCLK 1 DOUT DSEL DCLK 1 DOUT MSB B16 Audio Buffer 4109E–8051–06/03 ...
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MP3 Buffer Interrupt Request MP3 Song Playing AT8xC51SND1C 76 Table 83. Sample Duplication Factor DUP1 DUP0 Factor sample duplication, DAC rate = 8 kHz (C51 rate One sample duplication, DAC rate = 16 kHz (2 ...
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Figure 53. MP3 Mode Audio Configuration Flow Voice or Sound Playing Figure 54. Voice or Sound Mode Audio Flows Voice/Song Mode Configuration Program Audio Clock Configure Interface HLR = X DSIZ = X POL = X JUST4:0 = XXXXXb DUP1:0 ...
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Registers AT8xC51SND1C 78 Table 84. AUDCON0 Register AUDCON0 (S:9Ah) – Audio Interface Control Register JUST4 JUST3 JUST2 Bit Bit Number Mnemonic Description Audio Stream Justification Bits JUST4:0 Refer to Section "Data Converter", page ...
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Table 86. AUDSTA Register AUDSTA (S:9Ch Read Only) – Audio Interface Status Register SREQ UDRN AUBUSY Bit Bit Number Mnemonic Description Audio Sample Request Flag Set in C51 audio source mode when the audio interface request ...
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Universal Serial Bus USB Mass Storage Class Bulk-Only Transport USB Device Firmware Upgrade (DFU) AT8xC51SND1C 80 The AT8xC51SND1C implements a USB device controller supporting full speed data transfer. In addition to the default control endpoint 0, it provides 2 other ...
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Description Clock Controller 4109E–8051–06/03 The USB device controller provides the hardware that the AT8xC51SND1C needs to interface a USB link to a data flow stored in a double port memory. It requires a 48 MHz reference clock provided by the ...
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Serial Interface Engine (SIE) Figure 57. SIE Block Diagram End of Packet Start of Packet D+ D- USB CLOCK AT8xC51SND1C 82 The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and unstuffing. • CRC ...
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Function Interface Unit (UFI) Figure 58. UFI Block Diagram 12 MHz DPLL Endpoint Control To/From SIE Figure 59. USB Typical Transaction Load OUT Transactions: OUT DATA0 (n Bytes) HOST UFI C51 IN Transactions: HOST IN UFI NACK Endpoint FIFO Write ...
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Configuration General Configuration Endpoint Configuration Figure 60. Endpoint Selection UEPSTA0 Endpoint 0 UEPSTA2 Endpoint 2 AT8xC51SND1C 84 • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See “Clock Controller” ...
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Endpoint enable Before using an endpoint, this must be enabled by setting the EPEN bit in the UEP- CONX register. An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint 0) ...
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Read/Write Data FIFO Read Data FIFO Write Data FIFO FIFO Mapping Figure 61. Endpoint FIFO Configuration UEPSTA0 Endpoint 0 UEPSTA2 Endpoint 2 AT8xC51SND1C 86 • Endpoint FIFO reset Before using an endpoint, its FIFO should be reset. This action resets ...
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Bulk/Interrupt Transactions Bulk/Interrupt OUT Transactions in Standard Mode 4109E–8051–06/03 Bulk and Interrupt transactions are managed in the same way. Figure 62. Bulk/Interrupt OUT transactions in Standard Mode HOST OUT DATA0 (n Bytes) OUT DATA1 OUT DATA1 DATA1 OUT An endpoint ...
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Bulk/Interrupt OUT Transactions in Ping-pong Mode AT8xC51SND1C 88 Figure 63. Bulk/Interrupt OUT Transactions in Ping-pong Mode HOST OUT DATA0 (n Bytes) ACK DATA1 (m Bytes) OUT ACK OUT DATA0 (p Bytes) ACK An endpoint should be first enabled and configured ...
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Bulk/Interrupt IN Transactions in Standard Mode 4109E–8051–06/03 If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is ...
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Bulk/Interrupt IN Transactions in Ping-pong Mode AT8xC51SND1C 90 Figure 65. Bulk/Interrupt IN transactions in Ping-pong mode UFI HOST IN NACK IN DATA0 (n Bytes) ACK TXCMPL IN DATA1 (m Bytes) ACK TXCMPL IN DATA0 (p Bytes) ACK An endpoint should ...
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Control Transactions Setup Stage Data Stage: Control Endpoint Direction Status Stage 4109E–8051–06/03 The DIR bit in the UEPSTAX register should Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in ...
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Isochronous Transactions Isochronous OUT Transactions in Standard Mode Isochronous OUT Transactions in Ping-pong Mode AT8xC51SND1C 92 An endpoint should be first enabled and configured before being able to receive Isochro- nous packets. When an OUT packet is received on an ...
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Isochronous IN Transactions in Standard Mode Isochronous IN Transactions in Ping-pong Mode 4109E–8051–06/03 If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet ...
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Miscellaneous USB Reset STALL Handshake Start of Frame Detection Frame Number Data Toggle Bit AT8xC51SND1C 94 The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This ...
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Suspend/Resume Management Suspend Resume 4109E–8051–06/03 The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is ...
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Upstream Resume Figure 67. Example of REMOTE WAKEUP Management SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND state upstream RESUME sent AT8xC51SND1C 96 A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose. W ...
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USB Interrupt System Interrupt System Priorities D+ USB Controller D- USB Interrupt Control System 4109E–8051–06/03 Figure 68. USB Interrupt Control System EUSB EA IE1.6 IE0.7 Interrupt Enable Table 1. Priority Levels IPHUSB IPLUSB shown in ...
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Figure 69. USB Interrupt Control Block Diagram Endpoint 0..2) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 ...
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Registers 4109E–8051–06/03 Table 90. USBCON Register USBCON (S:BCh) – USB Global Control Register USBE SUSPCLK SDRMWUP Bit Bit Number Mnemonic Description USB Enable Bit Set this bit to enable the USB controller. 7 USBE Clear this bit ...
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AT8xC51SND1C 100 Table 91. USBADDR Register USBADDR (S:C6h) – USB Address Register FEN UADD6 UADD5 Bit Bit Number Mnemonic Description Function Enable Bit Set to enable the function. The device firmware should set this bit after it ...
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Table 93. USBIEN Register USBIEN (S:BEh) – USB Global Interrupt Enable Register EWUPCPU Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not ...
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AT8xC51SND1C 102 Table 95. UEPCONX Register UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM EPEN NAKIEN NAKOUT Bit Bit Number Mnemonic Description Endpoint Enable Bit Set to enable the endpoint according ...
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Table 96. UEPSTAX Register UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM DIR RXOUTB1 STALLRQ Bit Bit Number Mnemonic Description Control Endpoint Direction Bit This bit is relevant ...
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AT8xC51SND1C 104 Bit Bit Number Mnemonic Description Stall Handshake Request Bit 5 STALLRQ Set to send a STALL answer to the host for the next handshake. Clear otherwise. TX Packet Ready Control Bit Set after a packet has been written ...
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Table 97. UEPRST Register UEPRST (S:D5h) – USB Endpoint FIFO Reset Register Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not ...
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AT8xC51SND1C 106 Table 99. UEPIEN Register UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do ...
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Table 101. UBYCTX Register UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM BYCT6 BYCT5 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bits ...
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AT8xC51SND1C 108 Table 103. UFNUMH Register UFNUMH (S:BBh, Read-only) – USB Frame Number High Register CRCOK Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. ...
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MultiMedia Card Controller Card Concept Card Signals Card Registers Bus Concept 4109E–8051–06/03 The AT8xC51SND1C implements a MultiMedia Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged ...
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Bus Lines Bus Protocol AT8xC51SND1C 110 The MultiMedia Card bus architecture requires all cards to be connected to the same set of lines. No card has an individual connection to the host or other devices, which reduces the connection costs ...
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Figure 71. (Multiple) Block Read Operation MCMD Command MDAT Block Read Operation Figure 72. Sequential Write Operation MCMD Command MDAT Figure 73. Multiple Block Write Operation MCMD Command Response MDAT Figure 74. No Response and No Data Operation MCMD MDAT ...
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Response Token Format AT8xC51SND1C 112 Table 105. Command Token Format Bit Position 47 46 Width (Bits Value ‘0’ ‘1’ Transmission Start bit Description bit There are five types of response tokens (R1 to R5). As shown in Figure ...
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Data Packet Format Clock Control 4109E–8051–06/03 Table 108. R3 Response Format (OCR Register) Bit Position 47 46 Width (bits Value ‘0’ ‘0’ Transmission Start bit Description bit Table 109. R4 Response Format (Fast I/O) Bit Position 47 46 ...
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Description Figure 78. MMC Controller Block Diagram OSC Generator CLOCK Internal Bus Clock Generator AT8xC51SND1C 114 required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. Following is a list of ...
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Figure 79. MMC Clock Generator and Symbol OSC CLOCK MMCEN MMCON2.7 Figure 80. Configuration Flow 4109E–8051–06/03 Controller Clock MMCLK MMCD7:0 MMC Clock As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system clock. The MMC ...
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Command Line Controller Figure 81. Command Line Controller Block Diagram TX Pointer 5-Byte FIFO MMCMD CTPTR Write MMCON0.4 CFLCK MMSTA.0 Command Transmitter RX Pointer 17 - Byte FIFO MMCMD CRPTR Read MMCON0.5 Command Receiver Command Transmitter AT8xC51SND1C 116 As shown ...
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Command Receiver 4109E–8051–06/03 User may abort command loading by setting and clearing the CTPTR bit in MMCON0 register which resets the write pointer to the transmit FIFO. Figure 82. Command Transmission Flow Command Transmission Configure Response RESPEN = X RFMT ...
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Data Line Controller Figure 83. Data Line Controller Block Diagram MMINT.0 MMINT.2 F1EI F1FI 8-Byte TX Pointer FIFO 1 DTPTR MMCON0.6 16-Byte FIFO MMDAT RX Pointer DRPTR 8-Byte MMCON0.7 FIFO 2 F2EI F2FI MMINT.1 MMINT.3 FIFO Implementation Data Configuration AT8xC51SND1C ...
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Data Transmitter Configuration Data Loading Data Transmission End of Transmission Busy Status 4109E–8051–06/03 Figure 84. Data Controller Configuration Flows Data Stream Configuration Configure Format DFMT = 0 For transmitting data to the card user must first configure the data controller ...
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Figure 85. Data Stream Transmission Flows Data Stream Transmission FIFOs Filling write 16 data to MMDAT Start Transmission DATEN = 1 DATEN = 0 FIFO Empty? F1EI or F2EI = 1? FIFO Filling write 8 data to MMDAT No More ...
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Figure 86. Data Block Transmission Flows Data Block Transmission FIFOs Filling write 16 data to MMDAT Start Transmission DATEN = 1 DATEN = 0 FIFO Empty? F1EI or F2EI = 1? FIFO Filling write 8 data to MMDAT No More ...
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Data Reading Figure 87. Data Stream Reception Flows Data Stream Reception FIFO Full? F1FI or F2FI = 1? FIFO Reading read 8 data from MMDAT No More Data To Receive? Send STOP Command a. Polling mode AT8xC51SND1C 122 This time-out ...
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Figure 88. Data Block Reception Flows Data Block Reception Start Transmission DATEN = 1 DATEN = 0 FIFO Full? F1EI or F2EI = 1? FIFO Reading read 8 data from MMDAT No More Data To Receive? a. Polling mode Flow ...
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Interrupt Description Figure 89. MMC Controller Interrupt System MCBI MMINT.7 EORI MMINT.6 EOCI MMINT.5 EOFI MMINT.4 F2FI MMINT.3 F1FI MMINT.2 F2EI MMINT.1 F1EI MMINT.0 AT8xC51SND1C 124 As shown in Figure 89, the MMC controller implements eight interrupt sources reported in ...
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Registers 4109E–8051–06/03 Table 112. MMCON0 Register MMCON0 (S:E4h) – MMC Control Register DRPTR DTPTR CRPTR Bit Bit Number Mnemonic Description Data Receive Pointer Reset Bit 7 DRPTR Set to reset the read pointer of the data ...
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AT8xC51SND1C 126 Table 113. MMCON1 Register MMCON1 (S:E5h) – MMC Control Register BLEN3 BLEN2 BLEN1 Bit Bit Number Mnemonic Description Block Length Bits BLEN3:0 Refer to Table 111 for bits description. Do not ...
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Table 115. MMSTA Register MMSTA (S:DEh Read Only) – MMC Control and Status Register CBUSY Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. ...
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AT8xC51SND1C 128 Table 116. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register MCBI EORI EOCI Bit Bit Number Mnemonic Description MMC Card Busy Interrupt Flag Set by hardware when the card enters or exits its ...
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Table 117. MMMSK Register MMMSK (S:DFh) – MMC Interrupt Mask Register MCBM EORM EOCM Bit Bit Number Mnemonic Description MMC Card Busy Interrupt Mask Bit 7 MCBM Set to prevent MCBI flag from generating an MMC ...
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AT8xC51SND1C 130 Table 119. MMDAT Register MMDAT (S:DCh) – MMC Data Register MD7 MD6 MD5 Bit Bit Number Mnemonic Description MMC Data Byte MD7:0 Input (write) or output (read) register of the data FIFO. ...
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IDE/ATAPI Interface Description 4109E–8051–06/03 The AT8xC51SND1C provides an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16- bit data transfer (read or write) between the AT8xC51SND1C and the ...
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IDE Device Connection AT8xC51SND1C 132 Figure 91. IDE Write Waveforms CPU Clock ALE ( DPL or Ri (2),( DPH or P2 Notes: 1. signal may be stretched using M0 bit in AUXR register When ...
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Registers 4109E–8051–06/03 Table 121. External Data Memory Interface Signals Signal Name Type Description Address Lines A15:8 I/O Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. Address/Data Lines AD7:0 I/O Multiplexed lower ...
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Serial I/O Port Mode Selection Baud Rate Generator Timer 1 AT8xC51SND1C 134 The serial I/O port in the AT8xC51SND1C provides both synchronous and asynchro- nous communication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode ...
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Internal Baud Rate Generator Synchronous Mode (Mode 0) Transmission (Mode 0) 4109E–8051–06/03 When using the Internal Baud Rate Generator, the Baud Rate is derived from the over- flow of the timer. As shown in Figure 95 the Internal Baud Rate ...
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Reception (Mode 0) Baud Rate Selection (Mode 0) AT8xC51SND1C 136 Figure 97. Transmission Waveforms (Mode 0) TXD Write to SBUF RXD start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI ...
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Asynchronous Modes (Modes 1, 2 and 3) Mode 1 Modes 2 and 3 Transmission (Modes 1, 2 and 3) Reception (Modes 1, 2 and 3) 4109E–8051–06/03 The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure ...
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Framing Error Detection (Modes 1, 2 and 3) Baud Rate Selection (Modes 1 and 3) AT8xC51SND1C 138 Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON ...
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Table 124. Internal Baud Rate Generator Value MHz PER Baud Rate SPD SMOD1 BRL 115200 - - 57600 - - 38400 1 1 246 19200 1 1 236 9600 1 1 217 4800 1 1 178 F ...
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Multiprocessor Communication (Modes 2 and 3) Automatic Address Recognition Given Address AT8xC51SND1C 140 Figure 108. Baud Rate Formula (Mode 2) Baud_Rate= Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit ...
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Broadcast Address Reset Address 4109E–8051–06/03 The following is an example of how to use given addresses to address different slaves: Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 0X0Xb Slave B:SADDR = 1111 0011b SADEN = ...
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Interrupt SMOD0 = X SMOD0 = 1 SMOD0 = 0 SMOD0 = 1 SMOD0 = 1 AT8xC51SND1C 142 The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and “end of transmission” (TI ...
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Registers 4109E–8051–06/03 Table 125. SCON Register SCON (S:98h) – Serial Control Register FE/SM0 OVR/SM1 SM2 Bit Bit Number Mnemonic Description Framing Error Bit To select this function, set SMOD0 bit in PCON register. FE Set by hardware ...
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AT8xC51SND1C 144 Table 126. SBUF Register SBUF (S:99h) – Serial Buffer Register SD7 SD6 SD5 Bit Bit Number Mnemonic Description Serial Data Byte SD7:0 Read the last data received by the serial I/O Port. ...
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Table 129. BDRCON Register BDRCON (S:92h) – Baud Rate Generator Control Register Bit Bit Number Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set ...
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Synchronous Peripheral Interface Figure 111. Typical Master SPI Bus Configuration Pn.z Pn.y Pn.x AT8xC51SND1C P4.0 P4.1 P4.2 Figure 112. Typical Slave SPI Bus Configuration SSn SS1 SS0 MASTER MISO MOSI SCK AT8xC51SND1C 146 The AT8xC51SND1C implements a Synchronous Peripheral Interface ...
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Description Master Mode Figure 113. SPI Master Mode Block Diagram MOSI/P4.1 MISO/P4.0 SCK/P4.2 SS#/P4.3 PER Bit Rate Generator CLOCK SPEN SPCON.6 Note: MSTR bit in SPCON is set to select master mode. 4109E–8051–06/03 The SPI controller interfaces with the C51 ...
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Slave Mode Figure 114. SPI Slave Mode Block Diagram MISO/P4.2 MOSI/P4.1 SCK/P4.2 SS/P4.3 Note: 1. MSTR bit in SPCON is cleared to select slave mode. Bit Rate AT8xC51SND1C 148 The SPI operates in slave mode when the MSTR bit in ...
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Data Transfer Figure 115. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO (From Slave) SS (to slave) Capture point 4109E–8051–06/03 Table 131. Serial Bit Rates ...
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Figure 116. Data Transmission Format (CPHA = 1) SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from master) MISO (from slave) SS (to slave) Capture point SS Management Error Conditions AT8xC51SND1C 150 1 2 ...
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Interrupt 4109E–8051–06/03 The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault” flags. As shown in Figure 118, these flags are combined toghether to appear as a single inter- rupt source for the C51 ...
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Configuration Master Configuration Slave Configuration Data Exchange Master Mode with Polling Policy AT8xC51SND1C 152 The SPI configuration is made through SPCON. The SPI operates in master mode when the MSTR bit in SPCON is set. The SPI operates in slave ...
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Master Mode with Interrupt 4109E–8051–06/03 Figure 120 shows the initialization phase and the transfer phase flows using the inter- rupt. Using this flow prevents any overrun error occurrence. The bit rate is selected according to Table 131. The transfer format ...
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Slave Mode with Polling Policy AT8xC51SND1C 154 Figure 121 shows the initialization phase and the transfer phase flows using the polling. The transfer format depends on the master controller. SPIF flag is cleared when reading SPDAT (SPSTA has been read ...
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Slave Mode with Interrupt Policy 4109E–8051–06/03 Figure 120 shows the initialization phase and the transfer phase flows using the interrupt. The transfer format depends on the master controller. Reading SPSTA at the beginning of the ISR is mandatory for clearing ...
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Registers AT8xC51SND1C 156 Table 132. SPCON Register SPCON (S:C3h) – SPI Control Register SPR2 SPEN SSDIS Bit Bit Number Mnemonic Description SPI Rate Bit 2 7 SPR2 Refer to Table 131 for bit rate description. SPI Enable ...
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Table 133. SPSTA Register SPSTA (S:C4h) – SPI Status Register SPIF WCOL - Bit Bit Number Mnemonic Description SPI Interrupt Flag 7 SPIF Set by hardware when an 8-bit shift is completed. Cleared by hardware when ...
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Two-wire Interface (TWI) Controller Description AT8xC51SND1C 158 The AT8xC51SND1C implements a TWI controller supporting the four standard master and slave modes with multimaster capability. Thus, it allows connection of slave devices like LCD controller, audio DAC, etc., but also external ...
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Figure 124. Complete Data Transfer on TWI Bus SDA MSB Slave Address SCL 1 S 4109E–8051–06/03 R/W ACK direction signal bit from receiver Clock Line Held Low While Serial Interrupts Are Serviced The four operating modes are: ...
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Bit Rate Master Transmitter Mode AT8xC51SND1C 160 The bit rate can be selected from seven predefined bit rates or from a programmable bit rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 142). The predefined ...
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Master Receiver Mode Slave Receiver Mode 4109E–8051–06/03 In the master receiver mode, a number of data Bytes are received from a slave transmit- ter (see Figure 126). The transfer is initialized as in the master transmitter mode. When the START ...
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Slave Transmitter Mode Miscellaneous States AT8xC51SND1C 162 In the slave transmitter mode, a number of data Bytes are transmitted to a master receiver (see Figure 128). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON ...
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Figure 125. Format and States in the Master Transmitter Mode Successful transmis- S sion to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data ...
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Figure 126. Format and States in the Master Receiver Mode Successful reception S from a slave transmitter 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data ...
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Figure 127. Format and States in the Slave Receiver Mode Reception of the own slave address and one or more data Bytes. All are acknowledged Last data Byte received is not acknowledged Arbitration lost as master and addressed as slave ...
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Figure 128. Format and States in the Slave Transmitter Mode Reception of the own slave address and transmission of one or more data Bytes. Arbitration lost as master and addressed as slave Last data Byte transmitted. Switched to not addressed ...
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Table 136. Status for Master Transmitter Mode Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT A START condition has Write SLA+W 08h been transmitted Write SLA+W A repeated START 10h condition has been Write SLA+R ...
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Table 137. Status for Master Receiver Mode Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT A START condition has Write SLA+R 08h been transmitted Write SLA+R A repeated START 10h condition has been Write SLA+W ...
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Table 138. Status for Slave Receiver Mode with Own Slave Address Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT No SSDAT action Own SLA+W has been 60h received; ACK has been returned No SSDAT action ...
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Table 139. Status for Slave Receiver Mode with General Call Address Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT General call address No SSDAT action has been received; 70h ACK has been No SSDAT action ...
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Table 140. Status for Slave Transmitter Mode Status of the TWI Bus Status and TWI Hardware Code SSSTA To/From SSDAT Write data Byte Own SLA+R has been A8h received; ACK has been returned Write data Byte Arbitration lost in Write ...
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Registers AT8xC51SND1C 172 Table 142. SSCON Register SSCON (S:93h) – Synchronous Serial Control Register SSCR2 SSPE SSSTA Bit Bit Number Mnemonic Description Synchronous Serial Control Rate Bit 2 7 SSCR2 Refer to Table 135 for rate description. ...
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Table 143. SSSTA Register SSSTA (S:94h) – Synchronous Serial Status Register SSC4 SSC3 SSC2 Bit Bit Number Mnemonic Description Synchronous Serial Status Code Bits 7:3 SSC4:0 Refer to Table 136 to Table 128 ...
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Analog to Digital Converter Description AT8xC51SND1C 174 The AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital con- verter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used ...
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Clock Generator Channel Selection Conversion Precision Configuration 4109E–8051–06/03 The ADC clock is generated by division of the peripheral clock (see details in section “X2 Feature”, page 12). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure ...
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Conversion Launching End Of Conversion AT8xC51SND1C 176 Figure 132. ADC Configuration Flow The conversion is launched by setting the ADSST bit in ADCON register, this bit remains set during the conversion. As soon as the conversion is started, it takes ...
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Registers 4109E–8051–06/03 Table 147. ADCON Register ADCON (S:F3h) – ADC Control Register ADIDL ADEN Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. ...
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AT8xC51SND1C 178 Table 149. ADDH Register ADDH (S:F5h Read Only) – ADC Data High Byte Register ADAT9 ADAT8 ADAT7 Bit Bit Number Mnemonic Description ADC Data ADAT9:2 8 Most Significant Bits of the 10-bit ...
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Keyboard Interface Description Power Reduction Mode 4109E–8051–06/03 The AT8xC51SND1C implement a keyboard interface allowing the connection matrix keyboard based on 4 inputs with programmable interrupt capability on both high or low level. These ...
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Registers AT8xC51SND1C 180 Table 151. KBCON Register KBCON (S:A3h) – Keyboard Control Register KINL3 KINL2 KINL1 Bit Bit Number Mnemonic Description Keyboard Input Level Bit KINL3:0 Set to enable a high level detection on ...
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Electrical Characteristics Absolute Maximum Rating Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin .................................... I per I/O Pin ................................................................. Power Dissipation ............................................................. 1 W Operating Conditions Ambient Temperature Under Bias........................ -40 ...
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Table 153. Digital DC Characteristics VDD = 2 -40 to +85°C Symbol Parameter AT89C51SND1C Operating Current I DD AT83C51SND1C Operating Current AT89C51SND1C Idle Mode Current I DL AT83C51SND1C Idle Mode Current AT89C51SND1C Power-Down Mode Current ...
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I I and I Test Conditions DD 4109E–8051–06/03 Figure 136. I Test Condition, Active Mode DD VDD RST (NC) X2 Clock Signal X1 VSS PVSS UVSS AVSS VSS All other pins are unconnected Figure 137. I Test Condition, ...
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Converter Oscillator & Crystal Schematic Parameters AT8xC51SND1C 184 Table 155 Converter DC Characteristics V = 2 -40 to +85° Symbol Parameter AV Analog Supply Voltage DD Analog ...
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Phase Lock Loop Schematic Parameters In System Programming Schematic Parameters 4109E–8051–06/03 Figure 140. PLL Filter Connection FILT Table 157. PLL Filter Characteristics V = 2 -40 to +85° Symbol Parameter R Filter Resistor ...
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AC Characteristics External 8-bit Bus Cycles Definition of Symbols Timings AT8xC51SND1C 186 Table 159. External 8-bit Bus Cycles Timing Symbol Definitions Signals A Address D Data In L ALE Q Data Out Test conditions: capacitive load ...
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Waveforms 4109E–8051–06/03 Table 161. External 8-bit Bus Cycle - Data Write AC Timings V = 2 -40 to +85° Symbol Parameter T Clock Period CLCL T ALE Pulse Width LHLL T Address Valid ...
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External IDE 16-bit Bus Cycles Definition of Symbols AT8xC51SND1C 188 Figure 143. External 8-bit Bus Cycle - Data Write Waveforms ALE T LHLL AVLL P0 A7:0 P2 Table 162. External IDE 16-bit Bus Cycles Timing Symbol Definitions ...
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Timings 4109E–8051–06/03 Test conditions: capacitive load on all pins= 50 pF. Table 163. External IDE 16-bit Bus Cycle - Data Read AC Timings V = 2 -40 to +85° Symbol Parameter T Clock ...
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Waveforms SPI Interface Definition of Symbols AT8xC51SND1C 190 Figure 144. External IDE 16-bit Bus Cycle - Data Read Waveforms ALE T LHLL T LLRL RD T RLAZ T T AVLL LLAX P0 A7:0 T AVRL T AVDV P2 A15:8 Note: ...
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Timings 4109E–8051–06/03 Test conditions: capacitive load on all pins= 50 pF. Table 166. SPI Interface Master AC Timing V = 2 -40 to +85° Symbol Parameter T Clock Period CHCH T Clock High ...
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Waveforms (input) (SSCPOL= 0) (input) (SSCPOL= 1) (input) MISO (output) MOSI (input) SS (input) SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) MISO (output) MOSI (input) AT8xC51SND1C 192 Figure 146. SPI Slave Waveforms (SSCPHA SLCH T T ...
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SS (output) SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) MOSI (input) MISO (output) SS (output) SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) MOSI (input) MISO (output) 4109E–8051–06/03 Figure 148. SPI Master Waveforms (SSCPHA CHCH T T ...
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Two-wire Interface Timings Waveforms START or Repeated START condition SDA (INPUT/OUTPUT) SCL (INPUT/OUTPUT) AT8xC51SND1C 194 Table 167. TWI Interface AC Timing V = 2 -40 to +85° Symbol Parameter T ; STA Start ...
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MMC Interface Definition of symbols Timings Waveforms 4109E–8051–06/03 Table 168. MMC Interface Timing Symbol Definitions Signals C Clock D Data In O Data Out Table 169. MMC Interface AC timings = -40 to +85°C, CL ≤ 100pF (10 cards) V ...
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Audio Interface Definition of symbols Timings Waveforms AT8xC51SND1C 196 Table 170. Audio Interface Timing Symbol Definitions Signals C Clock O Data Out S Data Select Table 171. Audio Interface AC timings V = 2 -40 ...
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Analog to Digital Converter Definition of symbols Characteristics Waveforms CLK ADEN Bit ADSST Bit 4109E–8051–06/03 Table 172. Analog to Digital Converter Timing Symbol Definitions Signals C Clock E Enable (ADEN bit) Start Conversion S (ADSST bit) Table 173. Analog to ...
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Flash Memory Definition of symbols Timings AT8xC51SND1C 198 Figure 154. Analog to Digital Converter Characteristics Code Out 1023 1022 1021 1020 1019 1018 Ideal Transfer curve LSB (ideal ...
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Waveforms External Clock Drive and Logic Level References Definition of symbols Timings Waveforms 4109E–8051–06/03 Figure 155. FLASH Memory - ISP Waveforms RST (1) ISP Note: 1. ISP must be driven through a pull-down resistor (see Section “In System Program- ming”, ...
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AT8xC51SND1C 200 Figure 158. AC Testing Input/Output Waveforms INPUTS V - 0.5 DD 0.7 V 0.3 V 0.45 V Note: 1. During AC testing, all inputs are driven at V logic 0. 2. Timing measurements are made on all outputs ...