AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 156

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Registers
156
AT8xC51SND1C
Table 132. SPCON Register
SPCON (S:C3h) – SPI Control Register
Reset Value = 0001 0100b
Note:
Number
SPR2
1 - 0
Bit
7
7
6
5
4
3
2
1. When the SPI is disabled, SCK outputs high level.
Mnemonic Description
SPR1:0
SPEN
SSDIS
MSTR
SPEN
CPOL
CPHA
SPR2
Bit
6
SPI Rate Bit 2
Refer to Table 131 for bit rate description.
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no
effect if CPHA = 0.
Clear to enable SS in both master and slave modes.
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.
SPI Clock Polarity Bit
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
SPI Rate Bits 0 and 1
Refer to Table 131 for bit rate description.
SSDIS
5
MSTR
4
(1)
CPOL
3
CPHA
2
SPR1
1
4109E–8051–06/03
SPR0
0