AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 172

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Registers
172
AT8xC51SND1C
Table 142. SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
Reset Value = 0000 0000b
Number
SSCR2
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
SSSTO
SSCR2
SSSTA
SSCR1
SSCR0
SSPE
SSPE
SSAA
SSI
Bit
6
Synchronous Serial Control Rate Bit 2
Refer to Table 135 for rate description.
Synchronous Serial Peripheral Enable Bit
Set to enable the controller.
Clear to disable the controller.
Synchronous Serial Start Flag
Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
Synchronous Serial Stop Flag
Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
Synchronous Serial Interrupt Flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if
SSGC set) is recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Master Transmitter Mode in progress
Slave Receiver Mode in progress
Slave Transmitter Mode in progress
Synchronous Serial Control Rate Bit 1
Refer to Table 135 for rate description.
Synchronous Serial Control Rate Bit 0
Refer to Table 135 for rate description.
SSSTA
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
This bit has no specific effect when in master transmitter mode.
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
5
SSSTO
4
SSI
3
SSAA
2
SSCR1
1
4109E–8051–06/03
SSCR0
0