AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 87

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Bulk/Interrupt
Transactions
Bulk/Interrupt OUT
Transactions in Standard
Mode
4109E–8051–06/03
Bulk and Interrupt transactions are managed in the same way.
Figure 62. Bulk/Interrupt OUT transactions in Standard Mode
An endpoint should be first enabled and configured before being able to receive Bulk or
Interrupt packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-
responding endpoint, store the number of data Bytes by reading the UBYCTX register. If
the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal
to 0 and no data has to be read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the
RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this end-
point. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will
answer a NAK handshake for each OUT requests.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct and the endpoint Byte counter contains the number of Bytes sent by the Host.
OUT
OUT
OUT
OUT
HOST
DATA0 (n Bytes)
DATA1
DATA1
DATA1
ACK
NAK
NAK
ACK
UFI
RXOUTB0
RXOUTB0
AT8xC51SND1C
Endpoint FIFO Read Byte 1
Endpoint FIFO Read Byte 2
Endpoint FIFO Read Byte n
Endpoint FIFO Read Byte 1
Clear RXOUTB0
C51
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