mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 37

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
15 - 12
6 - 4
3 - 1
Read/Write Address: 0001
Reset Value: 0000
15
Bit
10
0
11
9
8
7
0
14
0
BBPD2 - 0
LBPD2 - 0
LFP16C
Unused
BFP8C
LFP8C
LFP4c
Name
LC8C
BPE
13
0
H
12
0
H
Reserved. In normal functional mode, these bits MUST be set to zero.
Local 8M Output (C8o) Polarity Control: When this bit is low, the C8o falling edge
aligns with the frame boundary. When it is high, the C8o rising edge aligns with the
frame boundary.
Backplane Frame Pulse (FP8i) Polarity Control: When this bit is low, the input
frame pulse should have the negative frame pulse format; the frame pulse goes low
for 122ns at the frame boundary. When it is high, the input frame pulse should have
the positive frame pulse format; the frame pulse goes high for 122ns at the frame
boundary.
Local Frame Pulse (FP16o) Polarity Control: When this bit is low, the output frame
pulse has the negative frame pulse format. The frame pulse goes low for 61ns at the
frame boundary. When it is high, the output frame pulse has the positive frame pulse
format. The frame pulse goes high for 61ns at the frame boundary.
Local Frame Pulse (FP8o) Polarity Control: When this bit is low, the output frame
pulse has the negative frame pulse format. The frame pulse goes low for 122ns at the
frame boundary. When it is high, the output frame pulse has the positive frame pulse
format. The frame pulse goes high for 122ns at the frame boundary.
Local Frame Pulse (FP4o) Polarity Control: When this bit is low, the output frame
pulse has the negative frame pulse format. The frame pulse goes low for 244ns at the
frame boundary. When it is high, the output frame pulse has the positive frame pulse
format. The frame pulse goes high for 244ns at the frame boundary.
Backplane Block Programming Data: These bits refer to the value to be loaded into
the backplane connection memory (BCM) whenever the memory block programming
feature is activated. After the MBP bit in the control register is set to high and the BPE
bit is set to high, the contents of the bits BBPD2-0 are loaded into Bit 13 to Bit 15 of the
BCM. Bit 0-12 of the BCM are zeroed.
Local Block Programming Data: These bits refer to the value to be loaded into the
local connection memory, i.e. Local Connection Memory Low (LCML) and Local
Connection Memory High (LCMH), whenever the memory block programming feature
is activated. After the MBP bit in the control register is set to high and the BPE bit is
set to high, the contents of the bits LBPD0 is loaded into Bit 15 of the LCML and the
LBPD1 to LBPD2 are loaded into Bit 0 to Bit 1 of the LCMH. Bit 0 to Bit 14 of LCML
and Bit 2 to Bit 14 of LCMH are zeroed.
Block Programming Enable.: A zero to one transition of this bit enables the memory
block programming function. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR
register must be defined in the same write operation. Once the BPE bit is set to high,
the device requires two frames to complete the block programming. After the
programming function has finished, the BPE bit returns to low indicating the operation
is completed. When the BPE is high, the BPE or MBP can be set to low to abort the
programming operation. When BPE is high, the other bits in the BPR register must not
be changed for two frames to ensure a proper block programming operation.
Whenever the microprocessor writes a one to the BPE bit, the block programming
function is started, the user must maintain the same logical value to the other bits in
the BPR register to avoid any change in the device setting.
LC8C
Table 6 - Block Programming Register (BPR) Bits
11
BFP
8C
10
LFP
16C
9
Zarlink Semiconductor Inc.
LFP
8C
8
LFP
4C
7
BBPD
Description
6
2
BBPD
5
1
BBPD
4
0
LBPD
3
2
LBPD
2
1
LBPD
1
0
BPE
0
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