MT90868 Zarlink Semiconductor, Inc., MT90868 Datasheet
MT90868
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MT90868 Summary of contents
Page 1
... Microprocessor Interface and Internal Registers DS CS R/W A15-A0 DTA D15-D0 Figure 1 - Functional Block Diagram MT90868 Advance Information ISSUE 1 September 2001 Ordering Information MT90868AG 466 Ball-PBGA -40 to +85 C ODE LSTo0-63 LCSTo0-3 Local Timing Unit LSTi0-63 IC0-IC5 Test Port TMS TDI TDO TCK TRST ...
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... The local port has sixty-four input and sixty-four output streams which operate at 8.192Mb/s. The backplane port has sixty-four input and sixty-four output streams which operate at 16.384Mb/s or 32.768Mb/s. The MT90868 has features that are programmable on per-stream or per-channel basis including message mode, input ...
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... DT1 C8i A0 A13 D1 D5 _62 _63 BYPS BSTo BSTo SG1 TM2 TM1 AT1 A12 D0 D4 _60 _61 MT90868 LSTi LSTi LSTi LSTo LSTo LSTi LSTi LSTi LSTi _54 _53 _50 _47 _46 _47 ...
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... MT90868 Ball Signal Assignment Ball Ball Signal Name Number Number B5 A1 BSTo8 A2 BSTo9 BSTi13 B8 A4 BSTi11 A5 BSTi9 B9 B10 A6 BSTo6 B11 A7 BSTo3 A8 BSTo1 B12 B13 A9 BSTi6 B14 A10 BSTi3 A11 TDi B15 B16 A12 TCK B17 A13 TDo A14 LSTi62 B18 ...
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... GND LSTo28 M13 GND LSTo27 M14 GND LSTo26 M15 GND LSTi30 M16 GND LSTi27 M17 GND BSTo27 M22 VDD_CORE BSTo26 M23 LSTo23 MT90868 Ball Signal Name Number M24 LSTo22 M25 LSTi25 M26 LSTi24 N1 BSTo30 N2 BSTo31 N3 BSTi33 N4 BSTi32 N5 GND N10 GND N11 ...
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... MT90868 Ball Ball Signal Name Number Number P15 GND T10 P16 GND T11 P17 GND T12 P22 GND T13 P23 LSTo18 T14 P24 LSTo19 T15 P25 LSTi22 T16 P26 LSTi19 T17 R1 BSTo35 T22 R2 BSTo34 T23 R3 BSTi37 T24 R4 BSTi36 T25 R5 VDD_CORE T26 ...
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... AF11 SG1 BSTo56 AF12 TM2 BSTo59 AF13 TM1 BSTo63 AF14 AT1 BSTo62 AF15 A12 DT1 AF16 D0 C8i AF17 D4 CLKBYPS AF18 D8 A0 AF19 D12 A13 AF20 R/W D1 AF21 CS MT90868 Ball Signal Name Number AF22 FP4o AF23 FP8o AF24 FP16o AF25 LSTi0 AF26 LSTi1 7 ...
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... MT90868 Pin Description PBGA Ball Number E12, E15, E20, E7, G23, G4, J22, M22, M5, R22, R5, V22, Y23, Y4, AB11, AB13, AB15, AC20, AC4, AC7. D22, D5, E11, E16, E18, E23, E4, E9, H23, J5, L22, L5, N22, T22, T5, V5, W23, AB16, AB18, AB23, AB4, AB9, AC5. M15, M16, M17, N10, N11, ...
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... JTAG test logic. TDi Test Serial Data In (5V Input with internal pull-up): JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up resistor when it is not driven. MT90868 Description data bus lines (D0-D15) ...
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... MT90868 Pin Description (continued) PBGA Ball Number A13 B11 B13 D11 D9 D10 AF25, AF26, AE26, AE25, AD26, AD25, AC26, AC25, Y26, Y25, W26, V26, U26, W25, V25, U25,T26,T25, R26, P26, N26, R25, P25, N25, M26, M25, L26, K26, J26, L25, K25, J25, H26, ...
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... BSTo0 - 63 and LSTo0 - 63 serial outputs. When it is high, the BSTo0 - 63, LSTo0 - 63 and LCSTo0-3 are enabled. When it is low, the BSTo0 - 63 are tristated or driven high, the LSTo0 - 63 are tristated and the LCSTo0 - 3 are driven high. MT90868 Description 11 ...
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... MT90868 Pin Description (continued) PBGA Ball Number AD8 12 Name BIME Bit Interleaving Mode Enable (5V Tolerant Input with internal pull down): When BIME and the BMS bit in the control register are both high, the bit interleaving mode is enabled. See Figure 26 for the bit interleaving mode timing diagram ...
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... This feature is useful for transferring control and status information for external circuits or other ST-BUS devices. Functional Description A Functional Block Diagram of the MT90868 is shown in Figure designed to interface ST-BUS serial streams from a backplane source and ST-BUS serial streams from a local source. ...
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... MT90868 FP8i C8i Ch255 Channel 0 BSTi/BSTo0- (16Mb/s) FP8o C8o Channel 125 LSTi/LSTo0- (8Mb/s) Figure 4 - Backplane and Local Frame Pulse Alignment, Backplane Data Rate is 16Mb/s FP8i C8i Ch 511 Ch 0 BSTi/BSTo0-63 (32Mb/s) FP8o C8o Channel 126 LSTi/LSTo0- ...
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... Input Bit Delay Selection The MT90868 input bit delay features allow users to have more flexibility when designing the switch matrices at high speed, in which the delay lines are easily created on PCM highways which are Modes 16 ...
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... MT90868 connected to the switch matrix cards. Each input data stream can have its own input bit delay value programmed by the input delay registers. The local input delay registers (LIDR0 - LIDR21) are used to program the local input delay. The backplane input delay registers (BIDR0 - BIDR21) are used to program the backplane input delay ...
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... Bit Delay, 1/2 Ch0 Ch1 Bit Delay, 1 Ch1 Ch0 MT90868 Ch1 Ch1 Ch1 Ch1 Ch1 2 1 ...
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... MT90868 Local Input Channel Delay and Local Channel Output Advancement The MT90868 provides users with the capability of programming the local input channel delay and the local output channel advancement. The local input channel delay programming allows all local input streams to have a different frame boundary with respect to the local frame pulse (F8o) ...
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... Figure 15 - Block Programming Data in the Connection Memories Switching Paths The MT90868 provides users with four switching paths, namely backplane", "backplane-to-backplane" and "local-to- local". The switching configuration is controlled by programming the local connection and the backplane connection memories. The "backplane-to-local" switching path allows the ...
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... Note: Input Buffer = Local input channel delay buffer Output Buffer = Local output channel advancement buffer. Table 2 - Data Delay Through the Device via Different Switching Paths Microprocessor Interface The MT90868 provides a microprocessor port interface for non-multiplexed bus structures. This interface is compatible to Motorola non-multiplexed bus structure specification ...
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... Local Output Channel Advancement Register 27, H LOCAR27 003E Local Output Channel Advancement Register 28, H LOCAR28 003F Local Output Channel Advancement Register 29, H LOCAR29 0040 Local Output Channel Advancement Register 30, H LOCAR30 Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) MT90868 21 ...
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... MT90868 Internal Register A15-A0 0041 Local Output Channel Advancement Register 31, H LOCAR31 0042 Local Input Bit Delay Register 0, LIDR0 H 0043 Local Input Bit Delay Register 1, LIDR1 H 0044 Local Input Bit Delay Register 2, LIDR2 H 0045 Local Input Bit Delay Register 3, LIDR3 H 0046 ...
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... Stream Stream Stream Stream MT90868 and the "backplane-to-backplane" Channel Address (Channel 0 - 511 Channel # ...
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... When the bus cycle is ended, the DTA switches to the high impedance state. An external pull-up is required at this output. Local External Tristate Control The MT90868 allows users the flexibility to perform the per-channel tristate operation for the local interface when external drivers or buffers are used for the LSTo0-64 outputs. ...
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... See Table 5, the OSB bit description in the control register. Bit Error Rate Test The MT90868 offers users the Bit Error Rate (BER) test feature for the backplane and local interfaces. The circuitry of the BER test consists of a transmitter and a receiver on both interfaces which can transmit and receive the BER patterns independently ...
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... Figure 17 - Backplane Output Streams Availability for BER Test at 32Mb/s mode Device Initialization The RESET pin is a synchronous system reset signal that puts the MT90868 into its reset state. When RESET goes low, it disables the LSTo0-63 and LCSTo0-3 outputs and drives the BSTo0-63 outputs to high ...
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... The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDi to its TDo. • The Device Identification Register The JTAG device ID for the MT90868 is 0086814BH. Version<31:28>: 0000 Part No. <27:12>: 0000 1000 0110 1000 Manufacturer ID<11:1>: 0001 0100 101 LSB<0>: 1 ...
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... MT90868 Registers Description Read/Write Address: 0000 H Reset Value: 0000 BHIZ LOCAEN LICDEN 0 STBY Bit Name 15 BHIZ Backplane Tristate or Driven-High Control: When this bit is low, the backplane outputs support the per-channel tristate feature. When this bit is high, the backplane outputs support the per-channel driven high feature ...
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... MT90868 BMS MBP OSB MS2 MS1 LCSTo0 LSTo0 BSTo0 to to LSTo63 to BSTo63 LCSTo3 X HiZ Driven Driven High High X HiZ Driven Driven High High ...
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... MT90868 Read/Write Address: 0001 H Reset Value: 0000 LC8C Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 11 LC8C Local 8M Output (C8o) Polarity Control: When this bit is low, the C8o falling edge aligns with the frame boundary. When it is high, the C8o rising edge aligns with the frame boundary ...
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... LICD 0 273 272 271 270 LICD LICD LICD LICD 0 293 292 291 290 LICD LICD LICD LICD 0 313 312 311 310 Description MT90868 LICD LICD LICD LICD LICD LICD LICD LICD LICD LICD LICD LICD ...
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... MT90868 Read/Write Address: 0012 - 00021 H H Reset Value: 0000 LICDR16 0 LICD LICD LICD 336 335 334 LICDR17 0 LICD LICD LICD 356 355 354 LICDR18 0 LICD LICD LICD 376 375 374 LICDR19 0 LICD LICD LICD 396 395 394 LICDR20 0 LICD ...
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... LOCA LOCA LOCA LOCA 0 LOCA 293 292 291 290 286 LOCA LOCA LOCA LOCA 0 LOCA 313 312 311 310 306 Description MT90868 LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA 25 ...
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... MT90868 Read/Write Address: 0032 - 00041 H H Reset Value: 0000 LOCAR16 0 LOCA LOCA LOCA 336 335 334 LOCAR17 0 LOCA LOCA LOCA 356 355 354 LOCAR18 0 LOCA LOCA LOCA 376 375 374 LOCAR19 0 LOCA LOCA LOCA 396 395 394 LOCAR20 0 LOCA ...
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... LID LID LID LID4 LID 441 440 434 433 32 431 LID LID LID LID LID4 LID 471 470 464 463 62 461 Description MT90868 LID LID LID LID LID LID LID LID LID LID LID LID ...
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... MT90868 Read/Write Address: 0052 - 00057 H H Reset Value: 0000 LIDR16 0 LID LID LID 504 503 502 LIDR17 0 LID LID LID 534 533 532 LIDR18 0 LID LID LID 564 563 562 LIDR19 0 LID LID LID 594 593 592 LIDR20 0 LID ...
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... BID BID BID BID BID BID 141 140 134 133 132 131 BID BID BID BID BID BID 171 170 164 163 162 161 Description MT90868 LIDn2 LIDn1 LIDn0 ...
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... MT90868 Read/Write Address: 005E - 0006D H H Reset Value: 0000 BIDR6 0 BID BID BID 204 203 202 BIDR7 0 BID BID BID 234 233 232 BIDR8 0 BID BID BID 264 263 262 BIDR9 0 BID BID BID 294 293 292 BIDR10 0 BID ...
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... N MT90868 BIDn2 BIDn1 BIDn0 ...
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... MT90868 Read/Write Address: 006E - 00075 H H Reset Value: 0000 LOAR0 LOA LOA LOA LOA LOAR1 LOA LOA LOA LOA 151 150 141 140 LOAR2 LOA LOA LOA LOA 231 230 221 220 LOAR3 LOA LOA LOA LOA ...
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... BOA 531 530 521 520 511 BOA BOA BOA BOA BOA 611 610 601 600 591 Description 32.768Mb/s (bit 1 1/2 MT90868 BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA 110 ...
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... MT90868 Read/Write Address: 007E H Reset Value: 0000 BDS B5 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero BDSB5 - 0 Backplane Data Stream Address Bits for Stream B: The binary value of these bits refers to the backplane input data stream. ...
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... Description LBL6 LBL5 Description LBC LBC LBC LBC LBC LBC Description MT90868 LBR LBR LBR LBR LBR CA4 CA3 CA2 CA1 CA0 LBL4 LBL3 LBL2 LBL1 LBL0 5 4 ...
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... MT90868 Read/Write Address: 0084 H Reset Value: 0000 BBR BBR BBR BBR SA5 SA4 SA3 SA2 Bit Name 15 Unused Reserved. In normal functional mode, this bit MUST be set to zero BBRSA5 - 0 Backplane BER Receive Stream Address Bits: The binary value of these bits refers to the backplane input stream which receives the BER data ...
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... Description LTM1 LTM0 LMSC Bit in LCML MT90868 LCAB LCAB LCAB LCAB LCAB Per-Channel Operation Mode 0 'Backplane-to-local' switching . Per-Channel Operation Mode 0 'Local-to-local switching' 1 High Impedance 0 Msg Mode ...
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... MT90868 BSRC BTM BTM BSA BSA = Bit Name 15 BSRC Backplane Source Control Bit: When this bit is low, the "local-to-backplane" switching is enabled and the source is from the local input port. Backplane TM Bits: These two bits control the backplane outputs ...
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... 3.3V and are for design aid only: not guaranteed and not subject to production DD_IO † - Timing Parameter Measurement Voltage Levels Sym Level V 0.5V CT DD_IO V 0.7V HM DD_IO V 0.3V LM DD_IO MT90868 Min Max -0.5 2.5 -0.5 5.0 -0 0.5 DD -0.5 7 +125 . ) unless otherwise stated SS ‡ Typ Max ...
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... MT90868 AC Electrical Characteristics Characteristic 1 Backplane Frame Pulse Width 2 Backplane Frame Pulse Setup Time before C8i clock falling edge 3 Backplane Frame Pulse Hold Time from C8i clock falling edge 4 C8i Clock Period 5 C8i Clock Pulse Width High 6 C8i Clock Pulse Width Low ...
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... BFPH t t BCH Timing t FPW4 t FOSF4 t LCP4 t CH4 t FPW8 t FOSF8 t t LCL8 CH8 t FPW16 t FOSF16 t t CL16 CH16 Local Port Timing MT90868 BCP t BCL t t fC8i rC8i t FOHR4 t CL4 t t rC4o fC4o t FOHR8 t CP8 t t rC8o fC8o t FOHR16 t LCP16 t t rC16o ...
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... MT90868 AC Electrical Characteristics Characteristic 1 Input data sampling point for Bit 0, Bit 2, Bit 4 and Bit 6 2 Input data sampling point for Bit 1, Bit 3, Bit 5 and Bit 7 3 Backplane Serial Input Set-up Time 4 Backplane Serial Input Hold Time 5 Backplane Serial Output Delay for Bit 0, ...
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... Advance Information MT90868 51 ...
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... MT90868 AC Electrical Characteristics Characteristic 1 Input data sampling point for Bit 0 and Bit 4 2 Input data sampling point for Bit 1 and Bit 5 3 Input data sampling point for Bit 2 and Bit 6 4 Input data sampling point for Bit 3 and Bit 7 5 Backplane Serial Input Set-up Time ...
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... DZ ODE at 1.8V and V at 3.3V and are for design aid only: not guaranteed and not subject to DD_IO HiZ TT ODE Valid Data STo TT MT90868 ‡ Typ Max Units Notes 91 =30pF L t SIS t SIH V TT Bit6 V ...
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... MT90868 AC Electrical Characteristics Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS rising 7 Data setup from DTA Low on Read 8 Data hold on read 9 Valid write data setup 10 Data hold on write ...
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... TDIH t TDOD t 200 TRSTW t 500 RSTW t t TCKL TCKH t TCKP t TMSH t TDIH t TDOD Figure 24 - JTAG Test Port Timing Diagram t RSTW Figure 25 - Reset Pin Timing Diagram MT90868 Typ Max Units Notes =30pF =30pF =30pF L t TRSTW ...
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... MT90868 56 Advance Information Bit4 Ch6 Bit4 Ch7 Bit4 Ch5 Bit4 Ch4 Bit4 Ch6 Bit5 Ch7 Bit4 Ch5 Bit5 Ch6 Bit4 Ch4 Bit5 Ch5 Bit5 Ch7 Bit5 Ch6 Bit5 Ch4 Bit6 Ch7 Bit5 Ch5 Bit5 Ch4 Bit6 Ch6 Bit6 Ch5 Bit6 Ch7 ...
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... Advance Information MT90868 57 ...
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... MT90868 The MT90868 is available in a 466 Ball-PBGA (Plastic Ball Grid Array) package, body size 35mm x 35mm with 1.27 mm ball-pitch. The package has 466 balls which consist of 324 signal balls and 98 ground balls. TOP VIEW PIN #1 CORNER o 4.00*45 (4X) 30.00 REF TYP. C SEATING PLANE ...
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North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 Tel: +65 333 6193 Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) ...