mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 22

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

2.6
The block programming register (BPR) provides users with the capability of initializing the local and backplane
connection memories in two frames. The local connection memory is partitioned into local connection memory high
(LCMH) and the local connection memory low (LCML). Bit 13 - bit 15 of every backplane connection memory location
will be programmed with the pattern stored in bit 4 - bit 6 of the BPR register. Bit 15 of every LCML location and bit
0 - bit 1 of every LCMH location will be programmed with the pattern stored in bits 1 to 3 of the BPR register. The
other bit positions of the backplane connection memory, the local connection memory low and all bits of the local
connection memory high are loaded with zeros. See Figure 15 for the connection memory contents when the device
is in the block programming mode.
The block programming mode is enabled by setting the memory block program (MBP) bit of the control register to
22
Note:
Channel Delay = 2
Channel Advance = 2
Channel Advance = 1
Channel Delay = 0
Channel Delay = 1
Channel Advance =0
Note:
X = 0 to 63
(Default)
Y = 0 to 63
LSTiX
LSTiX
LSTiX
(Default)
Memory Block Programming
FP8o
C8o
LSToY
LSToY
LSToY
FP8o
C8o
3
3
3
2
2
2
Figure 14 - Local Output Channel Advancement Timing Diagram
3
3
3
1 0
1 0
1 0
2
2
2
1 0
1 0
1 0
Figure 13 - Local Input Channel Delay Timing Diagram
7
7
7
6
6
6
7
7
7
5
5
5
Ch 0
Ch127
Ch126
Delay = 1
6
6
6
4
4
4
5
5
5
Ch 0
3
3
3
4
Ch1
4
Ch2
4
2
2
2
3
3
3
1 0
1 0
1 0
2
2
2
Delay = 2
1 0
1 0
1 0
7
7
7
Zarlink Semiconductor Inc.
6
6
6
7
7
7
5
5
Ch 1
Ch 0
5
Ch127
6
6
6
4
4
4
Ch 1
5
5
5
3
3
3
Ch2
4
4
Ch3
4
2
2
2
3
3
3
1 0
1 0
1 0
2
2
2
1 0
1 0
1 0
7
6
5
Ch0
4
3
6
6
7
2
Ch126
5
Ch125
5
6
6
6
1 0
4
4
5
Ch126
5
5
Ch127
3
3
Ch0
4
4
4
2
2
3
3
3
1 0
1 0
2
2
2
Advance = 2
1 0
1 0
1 0
7
7
7
6
6
6
7
7
7
5
5
5
Ch127
Ch126
Ch125
6
6
6
Advance = 1
4
4
4
5
5
5
Ch127
3
3
3
Ch1
4
4
4
Ch0
2
2
2
3
3
3
Data Sheet
1 0
1 0
1 0
2
2
2
1 0
1 0
1 0
7 6
7 6
7 6
7 6
7 6
7 6