mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 30

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

control and the per-channel message and the normal modes.
In the switching mode, the contents of the backplane connection memory stream address bits (BSAB0 - BSAB5)
and channel address bits (BCAB0 - BCAB6) define the source information (stream and channel) of the time slot that
will be switched to the backplane BSTo streams. During the message mode, only the lower 8 least significant bits
of the backplane connection memory will be transferred to the BSTo pins.
4.3
The local connection memory controls the local interface switching configurations through the Local Mode Selection
Control (LMSC) bit. When this bit is low, the input source is from the backplane input port and the "backplane-to-
local" switching path can be configured. When it is high, the input source is from the local input port and the "local-
to-local" switching path can be configured. The local connection memory consists of two parts, namely, the Local
Connection memory Low (LCML) and the Local Connection Memory High (LCMH). Each of them is 16-bit wide.
Locations in the local connection memory are associated with particular LSTo output streams.
The LTM1 - LTM0 bits of each Local Connection Memory High (LCMH) determine the per-channel message mode,
the pre-channel tristate and the normal modes.
In the switching mode, the stream address bits (LSAB0 - LSAB5) and channel address bits (LCAB0 - LCAB8) of the
local connection memory low (LCML) define the source information (stream and channel) of the time slot that will be
switched to the local LSTo streams. During the message mode, only the lower 8 least significant bits of the Local
Connection Memory Low are transferred to the LSTo pins.
4.4
All connection memory content can be read from the microprocessor port. However, only limited data memory
contents can be read from the micro- processor port at any one time. The backplane data memory has 1,024
locations and the local data memory has 256 locations to support the data memory reads.
The Backplane Data Memory Read Selection register (BDMRSR) selects the two backplane input streams which
will be read (or monitored) from the microprocessor port. The selected backplane input streams are labelled as
Stream C and Stream D. The Local Data Memory Read Selection register (LDMRSR) selects the two local input
streams which will be read (or monitored) from the microprocessor port. The selected backplane input streams are
labelled as Stream E and Stream F.
Users need to program the BDMRSR and LDMRSR registers before the proper data memory read operations can
occur. See Tables 22 and 23 for the description of the memory read selection registers. Also, see Table 4 for the
microprocessor addresses required to access Stream C&D or Stream E&F. Refer to the MS0 - 2 bits in the control
registers for the selection of the data memory to be read from the microprocessor port.
4.5
The DTA pin of the microprocessor is driven low by the internal logic to indicate that a data bus transfer cycle is
completed. When the bus cycle is ended, the DTA switches to the high impedance state. An external pull-up is
required at this output.
4.6
The MT90868 allows users the flexibility to perform the per-channel tristate operation for the local interface when
external drivers or buffers are used for the LSTo0-64 outputs.
The device provides four output control signals, LCSTo0 - LCSTo3 which have the data rate of 16.384Mb/s with
8,192 control bits per frame. Each control bit position is corresponding to a specific output stream and channel
location as defined in the local connection memory. When the LTM0 and LTM1 bits in the LCMH are programmed
to tristate selected local output channels, the corresponding LCSTo control bits will set to high for the selected
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Local Connection Memory
Data Memory Read Operation
Data Transfer Acknowledge
Local External Tristate Control
Zarlink Semiconductor Inc.
Data Sheet