mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 15

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
1.0
The MT90868 can switch up to 32,768 × 8,192 channels while providing a rate conversion capability. It is designed
to switch 64 kb/s PCM or N X 64 kb/s data between the backplane and local switching applications. The device
maintains frame integrity in data applications and minimum throughput delay for voice application on a per channel
basis.
The backplane interface can operate at 16.384Mb/s or 32.768Mb/s on ST-BUS and is arranged in 125µs wide
frames that contain 256 or 512 channels respectively. A built-in rate conversion circuit allows users to interface
between backplane and local interfaces which operates at 8.192Mb/s.
By using Zarlink’s message mode capability, the microprocessor can access input and output time slots on a per
channel basis. This feature is useful for transferring control and status information for external circuits or other ST-
BUS devices.
1.1
A Functional Block Diagram of the MT90868 is shown in Figure 1. It is designed to interface ST-BUS serial streams
from a backplane source and ST-BUS serial streams from a local source.
1.2
In the ST-BUS mode, the C8i pin accepts a 8.192MHz clock for the frame pulse alignment. The FP8i is a 8kHz
frame pulse signal which goes low at the frame boundary for 122ns. The frame boundary is defined by the falling
edge of the C8i clock during the low cycle of the frame pulse. Figure 3 shows the backplane port timing diagram
with the data rate of 16Mb/s and 32Mb/s.
The BFP8C bit in the block programming mode register (BPR) allows the device to accept different frame pulse
formats. If the BFP8C bit in the block programming register is low, the device accepts a negative frame pulse. If the
BFP8C bit is high, the device accepts a positive frame pulse as described in Figure 3.
The device accepts the backplane frame pulse input and generates the local frame pulse outputs. When the 16Mb/s
or 32 Mb/s mode is selected for the backplane port, the delay between the backplane and local frame pulse signals
is two 16Mb/s or 32Mb/s backplane channels plus 10 cycles of C8i respectively. Figures 4 and 5 show the
backplane and local frame pulse alignment for the 16Mb/s and the 32Mb/s timing mode respectively.
1.3
The local frame pulses, FP4o, FP8o and FP16o are 8kHz output signals that have a pulse width of 244ns, 122ns
and 61ns respectively at the frame boundary. The frame boundary is defined by the falling edge of the C8o output
clock during the low cycle of the frame pulse FP8o. At the frame boundary, the falling edges of the C4o and C16o
output clocks are aligned with the falling edge of
In addition, the C8o clock can be inverted by programming the C8C bit to high in the BPR register. When the LFP4C,
LFP8C and LFP16C bits are programmed to high in the BPR register, the device will provide positive frame pulse
for the FP4o, FP8o and FP16o outputs. The local port timing diagram is shown in Figure 6.
Device Overview
Functional Description
Frame Alignment Timing
Local Interface Output Timing
Zarlink Semiconductor Inc.
the C8o output clock.
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