mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 33

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
4.8
The RESET pin is a synchronous system reset signal that puts the MT90868 into its reset state. When RESET goes
low, it disables the LSTo0-63 and LCSTo0-3 outputs and drives the BSTo0-63 outputs to high. It also clears the
internal device registers and the internal counters. See Figure 25 for the reset timing.
Upon powering up, the MT90868 must be initialized according to the following initialization sequences:
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4.9
The MT90868 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the
boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller. See Figure 24 for the JTAG
test port timing.
4.9.1
The Test Access Port (TAP) accesses the MT90868 test functions. It consists of four input pins and one output pin
as follows:
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Set the ODE pin to low to tristate the LSTo0- 63, LCSTo0-3 and BSTo0-63 outputs.
Set the TRST pin to low to disable the internal JTAG TAP controller,
Set RESET pin to low to reset the device, To ensure proper reset action, the reset pin must be held low for
longer than 500ns. A delay of 100µs must also be applied before the first microprocessor access is
performed after the RESET pin is set high, this delay is required for the initialization of the APLL.
Use the Block Programming mode as described in the Memory Block Programming section to initialize the
local and the backplane connection memories,
Set the ODE pin to high after the connection memories are programmed to release the tristate on LSTo0-
63, LCSTo0-3 and BSTo)-63 outputs.
Set bit 11, STBY, of the Control Register (CR) to high for normal functional mode.
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent in the functional mode. The TCK permits shifting of test data into or out of the
Boundary-Scan register cells concurrently with the operation of the device and without interfering with the
on-chip logic.
Test Mode Select Input (TMS)
The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not
driven from an external source.
Test Data Input (TDi)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDo)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
It resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven from an external
source.
Device Initialization
JTAG Support
Test Access Port (TAP)
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