mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet
mt90868ag2
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mt90868ag2 Summary of contents
Page 1
... Mux Connection Memory (32,768 locations) Microprocessor Interface and Internal Registers DS CS R/W A15-A0 DTA D15-D0 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. High Bandwidth Digital Switch Data Sheet Ordering Information MT90868AG 466 Ball-PBGA -40 to +85° C ODE LCSTo0-3 Local Timing Unit Test Port ...
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... The MT90868 has features that are programmable on per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay, high impedance output control for both local and backplane streams and the driven-high backplane output control. 2 Zarlink Semiconductor Inc. Data Sheet ...
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... DT1 C8i A0 A13 D1 _59 _63 _62 BYPS BSTo BSTo SG1 TM2 TM1 AT1 A12 D0 _60 _61 Zarlink Semiconductor Inc LSTi LSTi LSTi LSTi LSTo LSTo LSTi LSTi _57 _54 _53 _50 _47 _46 ...
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... B15 LSTi60 B16 LSTi58 B17 LSTi56 B18 LSTi55 B19 LSTi52 B20 LSTi49 B21 LSTo45 B22 LSTo44 B23 LSTi45 B24 LSTi43 B25 LSTi41 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number B26 LSTi40 C1 BSTo13 C2 BSTo12 C3 BSTi15 C4 BSTi12 C5 BSTo7 C6 BSTo4 C7 IC3 C8 BSTi7 ...
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... VDD_IO E17 GND E18 VDD_IO E19 GND E20 VDD_CORE E23 VDD_IO E24 LSTo34 E25 LSTo33 E26 LSTo32 F1 BSTi22 F2 BSTi21 F3 BSTi20 Zarlink Semiconductor Inc. Ball Signal Name Number F4 GND F23 GND F24 LSTi39 F25 LSTi38 F26 LSTi37 G1 BSTo17 G2 BSTo16 G3 BSTi23 G4 VDD_CORE G23 ...
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... LSTi29 L26 LSTi26 M1 BSTo29 M2 BSTo28 M3 BSTi30 M4 BSTi31 M5 VDD_CORE M10 GND M11 GND M12 GND M13 GND Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number M14 GND M15 GND M16 GND M17 GND M22 VDD_CORE M23 LSTo23 M24 LSTo22 M25 LSTi25 ...
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... VDD_IO T10 GND T11 GND T12 GND T13 GND T14 GND T15 GND T16 GND T17 GND T22 VDD_IO T23 LSTo15 Zarlink Semiconductor Inc. Ball Signal Name Number T24 LSTo14 T25 LSTi17 T26 LSTi16 U1 BSTo38 U2 BSTo39 U3 BSTi40 U4 BSTi41 U5 GND U10 GND ...
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... AB16 VDD_IO AB17 GND AB18 VDD_IO AB19 GND AB23 VDD_IO AB24 LSTo4 AB25 LSTo3 AB26 LSTo2 AC1 BSTi51 Zarlink Semiconductor Inc. Data Sheet Ball Signal Name Number AC2 BSTi52 AC3 BSTi53 AC4 VDD_CORE AC5 VDD_IO AC6 GND AC7 VDD_CORE AC8 FP8i ...
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... AE18 D9 AE19 D13 AE20 DTA AE21 DS AE22 C4o AE23 C8o AE24 C16o AE25 LSTi3 AE26 LSTi2 AF1 BSTo49 Zarlink Semiconductor Inc. Ball Signal Name Number AF2 BSTo51 AF3 BSTo52 AF4 BSTo55 AF5 BSTi60 AF6 BSTi61 AF7 BSTo57 AF8 BSTo58 AF9 BSTO60 ...
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... This input must be provided for any function to operate. CLKBYPS APLL Bypass clock (5V Tolerant Input): This pin accepts a 131.072MHz clock for device testing purpose. In normal operation, this input MUST be low. Zarlink Semiconductor Inc. Data Sheet Description supply has DD_IO should not "lead" the ...
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... Test Clock (5V Tolerant Input): Provides the clock to the JTAG test logic. TDi Test Serial Data In (5V Input with internal pull-up): JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up resistor when it is not driven. Zarlink Semiconductor Inc. Description 11 ...
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... In normal operation, this input MUST be connected to ground. IC5 In normal operation, this input MUST be connected to ground. LSTi0 - 63 Local Serial Input Streams (5V Tolerant Inputs): These inputs accept data rates of 8.192 Mb/s with 128 channels per stream. Zarlink Semiconductor Inc. Data Sheet Description ...
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... BSTo0 - 63 and LSTo0 - 63 serial outputs. When it is high, the BSTo0 - 63, LSTo0 - 63 and LCSTo0-3 are enabled. When it is low, the BSTo0 - 63 are tristated or driven high, the LSTo0 - 63 are tristated and the LCSTo0 - 3 are driven high. Zarlink Semiconductor Inc. Description 13 ...
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... See Figure 26 for the bit interleaving mode timing diagram. When it is low, the bit interleaving mode is disabled and the BMS bit in the control register selects the 16Mb/s or 32Mb/s mode for the backplane streams. Zarlink Semiconductor Inc. Data Sheet Description ...
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... In addition, the C8o clock can be inverted by programming the C8C bit to high in the BPR register. When the LFP4C, LFP8C and LFP16C bits are programmed to high in the BPR register, the device will provide positive frame pulse for the FP4o, FP8o and FP16o outputs. The local port timing diagram is shown in Figure 6. the C8o output clock. Zarlink Semiconductor Inc. 15 ...
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... Channel 126 Two (32Mb/s) channels + Ten C8i Cycles Channel 127 Zarlink Semiconductor Inc. Data Sheet Channel 255 Channel 510 Channel 511 ...
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... FP16o LFP16C = 0 FP16o LFP16C = 1 C16o (16.384MHz) Channel 0 LSTi/LSTo0- (8Mb/s) Channel Figure 6 - Local Port Timing Diagram Zarlink Semiconductor Inc. Channel 126 Channel 127 ...
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... BIDR21) are used to program the backplane input delay. See Tables 8, 12 and Tables 14, 15 for the descriptions of the LIDR and BIDR registers. BMS bit of the Control Register 0 1 Table 1 - Mode Selection for Backplane Streams 18 Modes Backplane Interface 16.384Mb/s BSTi0 - 63 and BSTo0 - 63 32.768Mb/s BSTi0 - 63 and BSTo0 - 63 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit 0 Bit Advancement, -1/4 Ch255 Bit 2 Bit 1 Bit 0 Bit 7 Bit Advancement, -1/2 Ch255 Bit 2 Bit 1 Bit 0 Bit 7 Bit Advancement, -3/4 Ch255 Bit 1 Bit 0 Bit 7 Zarlink Semiconductor Inc. Ch0 Bit 7 Bit 6 Ch0 Bit 7 Bit 6 Ch0 Bit 6 Ch0 Bit 6 Ch0 Bit 5 Bit 4 Bit 7 Bit 6 Ch0 Bit 6 ...
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... Bit Delay, 1 Ch0 Ch127 Ch127 Zarlink Semiconductor Inc. Data Sheet Ch0 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 Bit 5 Bit 4 Ch0 Bit 2 Bit 1 Bit 0 Bit 5 Bit 4 Bit 3 Ch0 Bit 2 Bit 1 Bit 0 Bit 5 Bit 4 Bit 3 Ch0 ...
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... Ch1 Bit Delay, 1 Ch0 Ch1 Zarlink Semiconductor Inc. Ch1 Ch1 Ch1 Ch2 Ch3 6 5 ...
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... Ch1 Ch2 Ch2 Ch3 Zarlink Semiconductor Inc. Data Sheet Ch126 Ch127 Ch125 Ch126 ...
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... Backplane Connection Memory (BCM Local Connection Memory Low (LCML Local Connection Memory High (LCMH) Zarlink Semiconductor Inc ...
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... Input Buffer ON Input Buffer OFF Output Buffer OFF Output Buffer ON OFF (LICDEN = 1) (LOCAEN = 0) (LOCAEN = 1) 3 Frames 3 Frames 1 Frame + Frames + Frames Zarlink Semiconductor Inc. Data Sheet Input Buffer ON Output Buffer ON (LICDEN = 0) (LICDEN = 1) (LOCAEN = 1) 2 Frames 3 Frames 3 Frames 4 Frames 2 Frames + Frames ...
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... A15 is low, then the registers are addressed by A14 shown in Table 3. If A15 is high, the remaining address input lines are used to select the data and connection memory positions corresponding to the serial input or output data streams as shown in Table 4. four control lines (CS, DS, R/W and DTA). Zarlink Semiconductor Inc. 25 ...
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... Local Input Channel Delay Register H 20, LICDR20 0017 Local Input Channel Delay Register H 21, LICDR21 0018 Local Input Channel Delay Register H 22, LICDR22 0019 Local Input Channel Delay Register H 23, LICDR23 Table 3 - Address Map for Internal Registers, when A15 = 0 26 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Input Bit Delay Register 10, H LIDR10 004D Local Input Bit Delay Register 11, H LIDR11 Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) Zarlink Semiconductor Inc. A15-A0 Internal Register 004E Local Input Bit Delay Register 12, H LIDR12 004F Local Input Bit Delay Register 13, ...
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... Local BER Count Register, LBCR H 0084 Backplane BER Start Receive H Register, BBSRR 0085 Backplane BER Length Register, H BBLR 0086 Backplane BER Count Register, H BBCR 0087 Reserved H 7FFF Reserved H Table 3 - Address Map for Internal Registers, when A15 = 0 (continued) Zarlink Semiconductor Inc. Data Sheet ...
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... Stream Stream Stream Stream Zarlink Semiconductor Inc. Channel Address (Channel 0 - 511 Channel # ...
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... Each control bit position is corresponding to a specific output stream and channel location as defined in the local connection memory. When the LTM0 and LTM1 bits in the LCMH are programmed to tristate selected local output channels, the corresponding LCSTo control bits will set to high for the selected 30 Zarlink Semiconductor Inc. Data Sheet ...
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... LTM1 - LTM0 bits to "11" or the BTM1 - BTM0 bits to "11" in the local and the Ch 126 126 Nine C8o cycles Zarlink Semiconductor Inc. Ch127 Ch127 which can start 31 ...
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... BER test mode. Figure 17 explains the details. When the backplane port is in the 16Mb/s mode, all backplane output streams are available. 32 ... , 56, 58, 60, 62. 57, 59, 61, 63. ... , , unless the output stream + Zarlink Semiconductor Inc. Data Sheet ≤ ≤ is enabled for (for ) ...
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... TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. • Test Reset (TRST) It resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven from an external source. Zarlink Semiconductor Inc. 33 ...
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... The JTAG device ID for the MT90868 is 0086814BH. Version<31:28>: 0000 Part No. <27:12>: 0000 1000 0110 1000 Manufacturer ID<11:1>: 0001 0100 101 LSB<0>: 1 4.9.4 BSDL A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to support the use of the IEEE 1149 test interface. Read/Write Address: 0000 H Reset Value: 0000 H 15 ...
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... Bit 0 and Bit 1 of the Local Connection Memory High and Bit 13 to Bit 15 of the Backplane Connection Memory. When it is low, the memory block programming mode is disabled. Refer to Figure 15 for details. Table 5 - Control Register (CR) Bits (continued PRST CBERB SBERB CBERL SBERL Description Zarlink Semiconductor Inc BMS MBP OSB MS2 MS1 0 MS0 ...
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... Active Active Zarlink Semiconductor Inc. Data Sheet BMS MBP OSB MS2 MS1 BSTo0 LCSTo0 to BSTo63 to LCSTo3 HiZ Driven Driven High High HiZ Driven Driven High High ...
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... BPR register to avoid any change in the device setting. Table 6 - Block Programming Register (BPR) Bits BFP LFP LFP LFP BBPD 8C 16C Description Zarlink Semiconductor Inc BBPD BBPD LBPD LBPD LBPD BPE 37 ...
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... LICD LICD LICD LICD LICD 293 292 291 290 286 0 LICD LICD LICD LICD LICD 313 312 311 310 306 Description Zarlink Semiconductor Inc. Data Sheet LICD LICD LICD LICD LICD LICD LICD LICD LICD ...
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... LICD LICD LICD LICD 614 613 612 611 610 0 LICD LICD LICD LICD LICD 634 633 632 631 630 Description Zarlink Semiconductor Inc LICD LICD LICD LICD LICD LICD 326 325 324 323 322 321 LICD LICD LICD ...
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... LOCA LOCA LOCA LOCA 0 LOCA 293 292 291 290 286 0 LOCA LOCA LOCA LOCA LOCA 313 312 311 310 306 Description Zarlink Semiconductor Inc. Data Sheet LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA LOCA ...
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... Data Sheet Zarlink Semiconductor Inc. 41 ...
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... LOCA LOCA LOCA LOCA 613 612 611 610 606 0 LOCA LOCA LOCA LOCA LOCA 633 632 631 630 626 Description Zarlink Semiconductor Inc. Data Sheet LOCA LOCA LOCA LOCA LOCA LOCA 325 324 323 322 321 320 LOCA LOCA ...
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... LID LID LID LID4 442 441 440 434 433 32 LID LID LID LID LID LID4 472 471 470 464 463 62 Description Zarlink Semiconductor Inc LID LID LID LID LID LID LID LID LID LID LID ...
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... Zarlink Semiconductor Inc. Data Sheet LID LID LID LID LID LID 491 490 484 483 482 481 LID LID LID LID LID LID 521 520 514 ...
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... Zarlink Semiconductor Inc. Corresponding Delay Bits LIDn3 LIDn2 LIDn1 ...
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... BID BID BID 141 140 134 133 132 131 BID BID BID BID BID BID 171 170 164 163 162 161 Description Zarlink Semiconductor Inc. Data Sheet BID BID BID BID BID BID BID BID ...
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... BID BID BID BID BID BID 622 621 620 614 613 612 Description Zarlink Semiconductor Inc BID BID BID BID BID BID 191 190 184 183 182 181 BID BID BID BID ...
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... N Zarlink Semiconductor Inc. Data Sheet BIDn2 BIDn1 BIDn0 ...
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... LOA LOA LOA LOA LOA LOA 620 611 610 601 600 591 Description 8.192Mb/s (bit 1/8 - 1/4 - 3/8 Zarlink Semiconductor Inc LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA ...
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... BOA BOA BOA BOA BOA BOA 611 610 601 600 591 590 Description 32.768Mb/s (bit 1 1/2 Zarlink Semiconductor Inc. Data Sheet BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA ...
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... BDS BDS BDS BDS BDS BDS Description LDS LDS LDS LDS LDS LDS Description Zarlink Semiconductor Inc BDS BDS BDS BDS BDS BDS BDS BDS BDS BDS ...
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... LBL6 LBL5 Description LBC LBC LBC LBC LBC LBC Description Zarlink Semiconductor Inc. Data Sheet LBR LBR LBR LBR LBR CA4 CA3 CA2 CA1 CA0 LBL4 LBL3 LBL2 ...
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... BBL8 BBL7 BBL6 BBL5 Description BBC BBC BBC BBC BBC BBC Description Zarlink Semiconductor Inc BBR BBR BBR BBR BBR CA4 CA3 CA2 CA1 CA0 BBL4 BBL3 BBL2 BBL1 ...
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... Description LTM1 LTM0 LMSC Bit in LCML Zarlink Semiconductor Inc. Data Sheet LCAB LCAB LCAB LCAB LCAB Per-Channel Operation Mode 0 'Backplane-to-local' switching . Per-Channel Operation Mode 0 'Local-to-local switching' ...
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... BSA BSA BSA BCA Description BTM1 BTM0 Per-Channel Operation Mode Tristate/Driven-High (See Bit 15 (BHIZ) in Table Zarlink Semiconductor Inc BCA BCA BCA BCA BCA Normal Output Msg Mode BER Test Mode 0 BCA B0 ...
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... Tristate/Driven-High (See Bit 15 (BHIZ) in Table BER Test Mode Symbol V DD_CORE V DD_IO V I_3V V I_5V Zarlink Semiconductor Inc. Data Sheet BCA BCA BCA BCA BCA Normal Output Msg Mode Min Max Units -0.5 2.5 -0.5 5 ...
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... DD_IO † - Timing Parameter Measurement Voltage Levels Sym Level V 0.5V CT DD_IO V 0.7V HM DD_IO V 0.3V LM DD_IO Zarlink Semiconductor Inc unless otherwise stated SS ‡ Typ Max 25 +85 1.8 1.89 3.3 3.6 3.3 V DD_IO 5.0 5.5 ) unless otherwise stated. ...
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... FOHR16 t 59 CP16 t 27 CH16 t 27 CL16 rC16o fC16o at 3.3V and are for design aid only: not guaranteed and not subject to production testing. DD_IO Zarlink Semiconductor Inc. Data Sheet ‡ Typ Max Units Notes 122 230 122 124 ns 61 ...
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... BFPW t BFPH t BCH Timing t FPW4 t FOSF4 t LCP4 t CH4 t FPW8 t FOSF8 t t LCL8 CH8 t FPW16 t FOSF16 t t CL16 CH16 Local Port Timing Zarlink Semiconductor Inc. t BCP t BCL t t fC8i rC8i t FOHR4 t CL4 t fC4o t FOHR8 t CP8 t rC8o t FOHR16 t LCP16 t rC16o t rC4o t fC8o t fC16o ...
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... SIH t 68 SOD0 t SOD2 t SOD4 t SOD6 t 7 SOD1 t SOD3 t SOD5 t SOD7 at 3.3V and are for design aid only: not guaranteed and not subject to production DD_IO Zarlink Semiconductor Inc. Data Sheet ‡ Typ Max Units Notes 107 108 73 =30pF L 12 ...
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... Data Sheet Figure 19 - Backplane Data Timing Diagram (16Mb/s Mode) Zarlink Semiconductor Inc. 61 ...
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... Bit5 Ch511 Ch0 Ch0 Ch0 Ch0 t SOD4 t SOD5 t SOD6 t SOD7 Bit0 Bit7 Bit6 Bit5 Bit7 Bit4 Ch511 Ch0 Ch0 Ch0 Ch0 Ch0 Zarlink Semiconductor Inc. Data Sheet ‡ Typ Max Units Notes 114.5 115.5 ns 83.6 84.6 ns 53.3 54.3 ns 22.8 23 103.5 108 ns C =30pF L 73 ...
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... DZ ODE at 3.3V and are for design aid only: not guaranteed and not subject to production testing. DD_IO HiZ TT ODE Valid Data STo TT Zarlink Semiconductor Inc. ‡ Typ Max Units Notes 91 12 =30pF L t SIS t SIH V TT ...
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... DD_IO , with timing corrected to cancel time taken to discharge L t CSS t RWS t ADS VALID ADDRESS t WDS t AKD Zarlink Semiconductor Inc. Data Sheet Max Units Test Conditions =30pF L ...
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... TDIH t TDOD t 200 TRSTW t 500 RSTW t t TCKL TCKH t TCKP t TMSH t TDIH Figure 24 - JTAG Test Port Timing Diagram t RSTW Figure 25 - Reset Pin Timing Diagram Zarlink Semiconductor Inc. Typ Max Units Notes =30pF =30pF =30pF ...
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... Bit6 Ch2 Bit6 Ch1 Bit6 Ch0 Bit7 Ch3 Bit7 Ch2 Bit7 Ch1 Bit7 Ch0 Bit0 Bit0 Bit0 Bit0 Bit1 Zarlink Semiconductor Inc. Data Sheet Bit4 Ch7 Bit4 Ch6 Bit4 Ch5 Bit4 Ch4 Bit5 Ch7 Bit5 Ch6 Bit5 Ch5 Bit5 Ch4 Bit6 ...
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... Data Sheet Figure 27 - Backplane and Local Frame Pulse Alignment Diagram for the Bit Interleaving Mode Zarlink Semiconductor Inc. 67 ...
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Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...