mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 35

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
BHIZ
15
Read/Write Address: 0000
Reset Value: 0000
Bit
12
11
10
9
8
7
6
5
4
LOCAEN
14
Unused
CBERB
SBERB
CBERL
SBERL
Name
PRST
STBY
BMS
MBP
H
LICDEN
13
Reserved. In normal functional mode, this bit MUST be set to zero.
StandBy: In normal functional mode, this bit MUST be set to one after power up.
PRBS Reset: When this bit is high, the output of the BER transmitter will be initialized.
Backplane Bit Error Rate Clear: When this bit is high, it resets the backplane internal bit
error counter and the content of the backplane bit error count register (BBCR) to zero.
Upon completion of the reset, set this bit to zero.
Backplane Bit Error Rate Test Start: When this bit is high, it enables the backplane
BER transmitter and receiver; starts the backplane bit error rate test. The bit error test
result is kept in the backplane bit error count (BBCR) register. Upon the completion of the
BER test, set this bit to zero.
Local Bit Error Rate Clear: When this bit is high, it resets the local internal bit error
counter and the content of the local bit error count register (LBCR) to zero. Upon
completion of the reset, set this bit to zero.
Local Start Bit Error Rate Test: When this bit is high, it enables the local BER
transmitter and receiver; starts the local bit error rate test. The bit error test result is kept
in the local bit error count (LBCR) register. Upon the completion of the BER test, set this
bit to zero.
Backplane Mode Select: When the BIME pin is low and this bit is low, it enables the
16Mb/s mode and BSTi0-63 and BSTo0-63 have data rate of 16.384Mb/s. When the
BIME pin is low and this bit is high, it enables the 32Mb/s mode and BSTi0-63 and
BSTo0-63 have data rate of 32.768Mb/s. When the BIME pin is high, set this bit to high to
enable the bit interleaving mode operation.
Memory Block Programming: When this bit is high, the connection memory block
programming mode is enabled to program Bit 15 of the Local Connection Memory Low,
Bit 0 and Bit 1 of the Local Connection Memory High and Bit 13 to Bit 15 of the Backplane
Connection Memory. When it is low, the memory block programming mode is disabled.
Refer to Figure 15 for details.
H
12
0
Table 5 - Control Register (CR) Bits (continued)
STBY
11
PRST
10
CBERB
Zarlink Semiconductor Inc.
9
SBERB
8
Description
CBERL
7
SBERL
6
BMS
5
MBP
4
OSB
3
MS2
2
MS1
1
MS0
0
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