mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 25

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
When the local input data streams pass through the local input channel delay buffer to perform the input channel
adjustment by setting the LICDEN bit to high, the device will add one more frame data to the "local-to-backplane"
and the "local-to-local" data switching paths. When the local output data streams pass through the local output
channel advancement buffer to perform the output channel adjustment by setting the LOCAEN bit to high, the
device will add one more frame data delay to the "backplane-to-local" and the "local-to-local" switching paths.
Table 2 describes the different delay throughput for the various data switching paths.
4.0
The MT90868 provides a microprocessor port interface for non-multiplexed bus structures. This interface is
compatible to Motorola non-multiplexed bus structure specification. The required microprocessor signals are the
16-bit parallel data bus (D15 - D0), 16-bit address bus (A15 - A0) and
See Figure 23 for details on the Motorola non-multiplexed bus timing.
The MT90868 synchronous microprocessor port provides access to the internal registers, the connection and the
data memories. All memory mapping locations are read/write accessible except the local and backplane bit error
rate count registers (LBCR and BBCR) and data memories which can only be read by the users.
4.1
The address bus of the microprocessor port interface selects the internal registers and the memories. If the address
bit, A15 is low, then the registers are addressed by A14 to A0 as shown in Table 3.
If A15 is high, the remaining address input lines are used to select the data and connection memory positions
corresponding to the serial input or output data streams as shown in Table 4.
Microprocessor Interface
Address Mapping of Registers and Memories
Zarlink Semiconductor Inc.
four control lines (CS, DS, R/W and DTA).
25