mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 23

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
high. When the block programming enable (BPE) bit of the BPR register is set to high, the block programming data
will be loaded into bits 13 to 15 of every backplane connection memory location and bits 15 of every local
connection memory low and bit 0 to bit 1 of every local connection memory high location. The other connection
memory bits are loaded with zeros. It takes two frames (250µs) to allow the backplane and local connection
memories to be loaded. Upon the completion of the memory block programming, the device resets the BPE bit to
low to indicating that the process is finished. See Table 6 for the bit assignment of the BPR register.
BBPD2
LBPD0
15
15
15
0
BBPD
14
14
14
0
0
1
BBPD0
13
13
13
0
0
Figure 15 - Block Programming Data in the Connection Memories
0
12
12
12
0
0
11
11
11
0
0
0
Local Connection Memory High (LCMH)
Backplane Connection Memory (BCM)
Local Connection Memory Low (LCML)
10
10
10
0
0
0
Zarlink Semiconductor Inc.
9
9
9
0
0
0
8
8
8
0
0
0
7
7
7
0
0
0
6
6
6
0
0
0
5
5
5
0
0
0
4
4
4
0
0
0
3
3
3
0
0
0
2
2
2
0
0
0
LBPD2
1
1
1
0
0
LBPD1
0
0
0
0
0
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