mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 19

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
Possible adjustment of the local input data streams, LSTi0 - LSTi63 is up to 7 3/4 bits. The resolution is 1/4 bit or
1/4 C8o cycle. For backplane, the possible adjustment of the input data streams, BSTi0 - BSTi63 is up to 7 3/4 bits
with a resolution of 1/4 bit (or 1/8 C8i clock cycle) when the input data rate is 16.384Mb/s. When the input data rate
is 32.768Mb/s, the possible adjustment is up to 7 1/2 bits with a resolution of 1/2 bit (or 1/8 C8i clock cycle). Figures
10, 11 and 12 describe the details of the input bit delay programming for the local and the backplane interfaces
respectively.
Bit Advancement = -1/8
Bit Advancement = -1/4
Bit Advancement = -3/8
Bit Advancement = 0
Bit Advancement = -1/4
Bit Advancement = -1/2
Bit Advancement = -3/4
Bit advancement = 0
Figure 8 - Backplane Output Advancement Timing Diagram when the Data Rate is 16Mb/s
Figure 7 - Local Output Advancement Timing Diagram when the Data Rate is 8Mb/s
(16.384Mb/s)
(Default)
LSToX
LSToX
LSToX
LSToX
(Default)
FP8o
C8o
BSToX
BSToX
BSToX
BSToX
FP8i
C8i
Bit 1
Bit 1
Bit 2
Bit 1
Ch127
Bit 2
Bit 1
Ch255
Ch127
Bit Advancement, -3/8
Bit 2
Ch255
Ch127
Bit Advancement, -1/4
Bit Advancement, -3/4
Bit 2
Ch255
Bit 1
Ch127
Bit Advancement, -1/8
Bit Advancement, -1/2
Bit 0
Ch255
Bit 1
Bit Advancement, -1/4
Zarlink Semiconductor Inc.
Bit 0
Bit 1
Bit 0
Bit 1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 6
Ch0
Bit 6
Ch0
Ch0
Bit 6
Ch0
Ch0
Bit 6
Ch0
Ch0
Bit 5
Ch0
Bit 5
Bit 6
Bit 6
Bit 5
Bit 6
Bit 5
Bit 6
Bit 4
Bit 4
Bit 4
Bit 4
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