mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 29

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
The Control Register (CR) and the Block Programming Register (BPR) control all the major functions of the device.
The Control Register (CR) and the Block Programming Register (BPR) should be programmed immediately after
system power up to establish the desired switching configuration as explained in the Frame Alignment Timing and
the Switching Configurations sections.
The Control Register is used to select Data or Connection Memory for microport operations through the memory
select bits. The register also enables the local input channel delay, the output channel advancement, the backplane
per-channel output tristate or per-channel driven-high control selection, the memory block programming mode and
the BER test.
The Block Programming Register consists of the block programming data bits (LPBD2 - LPBD0, BBPD2 - BBPD0)
and the block programming enable bit (BPE). The BPE bit allows users to program the entire backplane and local
connection memories. See Memory Block Programming section. The BPR register also controls the local and the
backplane frame pulse polarities.
4.2
The Backplane Connection Memory (BCM) is 16-bit wide. It controls the switching configuration of the backplane
interface through the Backplane Source Control (BSRC) bit. When this bit is low, the input source is from the local
input port and the "local-to-backplane" switching paths can be configured. When this bit is high, the input source is
from the backplane input port and the "backplane-to-backplane" switching paths can be configured. Locations in
the backplane connection memory are associated with particular BSTo streams.
The BTM1 - BTM0 bits of each backplane connection memory determine the per-channel tristate (or driven-high)
Notes:
1. Bit A15 must be high to access the data memory and connection memory positions. (A15 must be low to access registers.)
2. Channels 0 to 127 are used when serial stream is at 8.192Mb/s.
3. Channels 0 to 255 are used when serial stream is at 16.384Mb/s.
4. Channels 0 to 511 are used when serial stream is at 32.768Mb/s.
5. Stream C&D or Stream E&F are selected by the backplane data memory read selection register (BDMRSR) or the local data memory read
(Note 1)
selection register (LDMRSR) respectively. These streams are selected to support the microprocessor port data memory read operation.
A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
.
14
A
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
Backplane Connection Memory
13
A
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
12
A
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
Table 4 - Address Map for Memory Locations, when A15 = 1
Stream Address (Stream 0 - 63)
11
A
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
10
A
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
.
.
.
.
.
.
.
.
.
.
.
.
A
9
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
.
.
.
.
.
.
.
.
.
.
.
.
Stream 0, C or E (Note 5)
Stream 1, D or F (Note 5)
Stream 2
Stream 3
.
.
.
.
.
.
.
Stream 29
Stream 30
Stream 31
Stream 32
Stream 33
Stream 34
Stream 35
Stream 36
.
.
.
.
.
.
Stream 60
Stream 61
Stream 62
Stream 63
Zarlink Semiconductor Inc.
Stream #
A
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
.
.
.
.
.
.
.
.
.
A
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
.
.
.
.
.
.
.
.
.
A
6
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
.
.
.
.
.
.
.
.
.
A
5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
Channel Address (Channel 0 - 511)
.
.
.
.
.
.
.
.
.
A
4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
.
.
.
.
.
.
.
.
.
A
3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
.
.
.
.
.
.
.
.
.
A
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
.
.
.
.
.
.
.
.
.
A
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
.
.
.
.
.
.
A
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
.
.
.
.
.
.
.
.
.
Ch 0
Ch 1
Ch 2
Ch 3
.
.
.
Ch 124
Ch 125
Ch 126
Ch 127 (Note 2)
Ch 128
Ch 129
Ch 130
Ch 131
.
.
.
Ch 252
Ch 253
Ch 254
Ch 255 (Note 3)
Ch 256
Ch 257
.
.
.
Ch 510
Ch 511 (Note 4)
Channel #
29