mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 18

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

2.0
The MT90868 has two operation modes at different data rates for the backplane interface and one operation mode
for the local interface. The two operation modes for the backplane interface can be selected via the backplane mode
selection bit (BMS) in the Control Register (CR).
2.1
The backplane interface can be programmed to accept data streams of 16Mb/s or 32Mb/s. When BMS bit of the CR
register is low, the 16Mb/s mode is enabled, BSTi0-63 and BSTo0-63 have a data rate of 16.384Mb/s. When BMS
= 1, the 32Mb/s mode is enabled, BSTi0-63 and BSTo0-63 have a data rate of 32.768Mb/s. Table 1 describes the
data rates and mode selections for the backplane interface.
2.2
The local interface has one mode of operation which can only operate at the data rate of 8.192Mb/s.
2.3
The device allows users to advance individual backplane or local output streams with respect to the frame boundary.
This feature is useful in compensating variable output delays caused by various output loading conditions. Each
output stream can have its own advancement value programmed by the output advancement registers. The
backplane output advancement registers (BOAR0 to BOAR7) are used to program the backplane output
advancement. The local output advancement registers (LOAR0 to LOAR7) are used to program the local output
advancement. See Tables 17 and Table 19 for the descriptions of the LOAR and BOAR registers.
Possible adjustment for local is -1/8, -1/4 or -3/8 bit and the resolution is 1/8 bit (or 1/8 of C8o cycle). For backplane,
the possible adjustment is -1/4, -1/2 or -3/4 bit when the output data rate is 16.384Mb/s. When the backplane data
rate is 32.768Mb/s, the possible adjustment is -1/2, -1 or -1 1/2 bit. For both data rates, the resolution is 1/8 of C8i
cycle. The advancement is independent of the output data rate. Figures 7, 8 and 9 describe the details of the output
advancement programming for the local and the backplane interfaces respectively.
2.4
The MT90868 input bit delay features allow users to have more flexibility when designing the switch matrices at high
speed, in which the delay lines are easily created on PCM highways which are connected to the switch matrix cards.
Each input data stream can have its own input bit delay value programmed by the input delay registers. The local
input delay registers (LIDR0 - LIDR21) are used to program the local input delay. The backplane input delay
registers (BIDR0 - BIDR21) are used to program the backplane input delay. See Tables 8, 12 and Tables 14, 15 for
the descriptions of the LIDR and BIDR registers.
18
BMS bit of the Control Register
Switching Configuration
Backplane Interface
Local Interface
Output Bit Advancement Selection
Input Bit Delay Selection
0
1
Table 1 - Mode Selection for Backplane Streams
16.384Mb/s
32.768Mb/s
Modes
Zarlink Semiconductor Inc.
BSTi0 - 63 and BSTo0 - 63
BSTi0 - 63 and BSTo0 - 63
Backplane Interface
Data Sheet