mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 21

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

Data Sheet
2.5
The MT90868 provides users with the capability of programming the local input channel delay and the local output
channel advancement.
The local input channel delay programming allows all local input streams to have a different frame boundary with
respect to the local frame pulse (F8o). It is enabled when the LICDEN bit in the control register (CR) is high. The
local input channel delay registers (LICDR0 - LICDR31) allows the users to delay the input channel from 0 to 127
channel for every local input stream. Figure 13 describes the local channel delay timing with different delay values.
The local output channel advancement programming allows all local output streams to have a different frame
boundary with respect to the local frame pulse (F8o). It is enabled when the LOCAEN bit in the CR register is set
to high. The local output channel advancement registers (LOCAR0 - LOCAR31) allows the users to advance the
output channel from 0 to 127 channels for every local output stream. Figure 14 describes the local channel output
advancement timing with different channel advancement values.
Bit Delay = 1/2
Bit Delay = 0
Bit Delay = 1
(8.192MHz)
Figure 12 - Backplane Input Bit Delay Timing Diagram when the Data Rate is 32Mb/s
Figure 11 - Backplane Input Bit Delay Timing Diagram when the Data Rate is 16Mb/s
(32Mb/s)
Default
Local Input Channel Delay and Local Channel Output Advancement
(8kHz)
BSTiX
BSTiX
BSTiX
Bit Delay = 1/2
FP8i
Bit Delay = 0
Bit Delay = 2
C8i
(8.192MHz)
(16Mb/s)
Default
(8kHz)
BSTiX
BSTiX
BSTiX
FP8i
3
4
C8i
3
2
3
2
1 0
2
1 0
1 0
1
7
3
7
6
7
1
6
Bit Delay, 1/2
5
6
0
Bit Delay, 1
2
5
4
5
0
4
Ch0
3
4
1
7
Ch0
3
2
Ch0
3
7
2
Bit Delay, 1/2
1 0
2
6
0
1 0
Zarlink Semiconductor Inc.
1 0
6
7
5
7
7
Bit Delay, 2
6
7
5
6
5
4
6
6
5
4
5
4
Ch 0
4
Ch1
3
3
4
5
Ch0
Ch1
3
2
Ch1
3
3
2
1 0
2
4
2
1 0
2
1 0
Ch0
1
3
7
7
1
7
6
6
0
2
5
6
5
0
4
5
4
7
1
Ch2
3
4
Ch2
3
7
Ch2
2
3
2
0
6
1 0
2
1 0
6
1 0
7
5
7
7
5
6
7
Ch1
6
4
6
5
6
Ch1
5
4
4
5
4
3
5
Ch3
3
4
Ch3
3
3
Ch3
2
3
Ch1
2
2
4
1 0
2
1 0
2
1
1
3
1
0
2
0
1
7
7
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