mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 10

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

10
Pin Description
E12, E15, E20, E7, G23, G4, J22,
D22, D5, E11, E16, E18, E23, E4,
AC2, AC3, AD1, AD2, AD4, AD3,
M22, M5, R22, R5, V22, Y23, Y4,
T5, V5, W23, AB16, AB18, AB23,
C11, B10, C10, A10, C9, B9, A9,
AD5, AE5, AF5, AF6, AD6, AE6.
M15, M16, M17, N10, N11, N12,
M4, N4, N3, P3, P4, R4, R3, T4,
AB11, AB13, AB15, AC20, AC4,
A1, A2, B1, B2, C2, C1, D2, D1,
K2, K1, L2, L1, M2, M1, N1, N2,
AA2, AE1, AF1, AE2, AF2, AF3,
AE3, AE4, AF4, AE7, AF7, AF8,
E9, H23, J5, L22, L5, N22, T22,
R12, R13, R14, R15, R16, R17,
C8, B5, A5, B4, A4, C4, A3, B3,
AA3, W4, AB1, AB2, AB3, AC1,
B8, A8, B7, A7, C6, B6, A6, C5,
G2, G1, H4, H3, H2, H1, J1, J2,
P2, P1, R2, R1, T2, T1, U1, U2,
C3, D3, E3, E2, E1, F3, F2, F1,
P10, P11, P12, P13, P14, P15,
T16, T17, U10, U11, U12, U13,
G3, J4, J3, K4, K3, L3, L4, M3,
N13, N14, N15, N16, N17, N5,
U14, U15, U16, U17, U22, U5,
T10, T11, T12, T13, T14, T15,
V2, V1, W2, W1, Y2, Y1, AA1,
P16, P17, P22, P5, R10, R11,
AE8, AF9, AF10, AE10, AE9.
T3, U3, U4, V3, W3, Y3, V4,
PBGA Ball Number
AB4, AB9, AC5.
W22, W5.
AE12
AE13
AC7.
AC8
BSTo0 - 63
BSTi0 - 63
V
CLKBYPS
V
DD_CORE
V
Name
ss (GND)
FP8i
DD_IO
C8i
Zarlink Semiconductor Inc.
Power Supply for Core Logic Circuits: +1.8V
Power Supply for Pads: +3.3V. The V
to be either established before the power up of the
V
V
Ground
Backplane Serial Input Streams 0 to 63 (5V Tolerant
Inputs): In 16Mb/s mode, these pins accept serial TDM
data streams at 16.384 Mb/s with 256 channels per
stream. In 32Mb/s mode, these pins accept serial TDM
data streams at 32.768 Mb/s with 512 channels per
stream.
Backplane Serial Output Streams 0 to 63 (5V Tolerant
Three-state Outputs): In 16Mb/s mode, these pins have
data rate of 16.384 Mb/s with 256 channels per stream. In
32Mb/s mode, these pins have data rate of 32.768 Mb/s
with 512 channels per stream.
Frame Pulse Input (5V Tolerant Input): This pin accepts
the backplane frame pulse which is low for 122ns (one
8.192MHz period) at the frame boundary. The frame
pulse frequency is 8kHz.
Master Clock Input (5V Tolerant Input): This pin
accepts an 8.192MHz clock. The clock falling edge is
aligned with the backplane frame boundary. This input
must be provided for any function to operate.
APLL Bypass clock (5V Tolerant Input): This pin
accepts a 131.072MHz clock for device testing purpose.
In normal operation, this input MUST be low.
DD_CORE
DD_IO
by more than 0.3V.
supply or the V
Description
DD_CORE
should not "lead" the
DD_IO
Data Sheet
supply has