mt90868ag2 Zarlink Semiconductor, mt90868ag2 Datasheet - Page 34

• Manufacturer Part Number: mt90868ag2
• Description: 32,768 X 8,192 Channels High Bandwidth Digital Switch With Up To 128 Streams On Backplane And 128 Streams On Local And Data Rates From 8 To 32 Mbps
• Manufacturer: Zarlink Semiconductor

4.9.2
The MT90868 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four-
bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data register
path that is used to shift data between TDI and TDO during data register scanning.
4.9.3
As specified in IEEE 1149.1, the MT90868 JTAG Interface contains three test data registers:
•
•
•
Version<31:28>: 0000
Part No. <27:12>: 0000 1000 0110 1000
Manufacturer ID<11:1>: 0001 0100 101
LSB<0>: 1
4.9.4
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to support the use of
the IEEE 1149 test interface.
34
BHIZ
15
Read/Write Address: 0000
Reset Value: 0000
Bit
15
14
13
The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT90868 core logic.
The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDi to its TDo.
The Device Identification Register
The JTAG device ID for the MT90868 is 0086814BH.
LOCAEN
14
LOCAEN
LICDEN
Name
BHIZ
Instruction Register
Test Data Register
BSDL
H
LICDEN
13
Backplane Tristate or Driven-High Control: When this bit is low, the backplane outputs
support the per-channel tristate feature. When this bit is high, the backplane outputs
support the per-channel driven high feature.
Local Output Channel Advancement Enable: When this bit is high, the Local Output
Channel Advancement is enabled and the local output data will pass through the local
output channel advancement buffer as shown in Figure 1. The local output channel
advancement registers (LOCAR31 - LOCAR0) control the channel advancement from 0
to 127 channels. When this bit is low, the channel advancement is disabled (default
condition) and the local output data will bypass the local output channel advancement
buffer.
Local Input Channel Delay Enable: When this bit is high, the Local Input Channel
Advancement is enabled and the local input data will pass through the local input channel
delay buffer as shown in Figure 1. The local input channel delay registers (LICDR31 -
LICDR0) control the channel delay from 0 to 127 channels. When this bit is low, the
channel delay is disabled (default condition) and the local input data will bypass the local
input channel delay buffer.
H
12
0
STBY
11
Table 5 - Control Register (CR) Bits
PRST
10
CBERB
Zarlink Semiconductor Inc.
9
SBERB
8
Description
CBERL
7
SBERL
6
BMS
5
MBP
4
OSB
3
MS2
Data Sheet
2
MS1
1
MS0
0